Interface Circuit for ADC-Free Analog Neural Network Layers
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Solution Overview
Problem
Existing neural network implementations require analog-to-digital converters (ADCs) between successive layers, which occupy significant chip area and consume power, limiting the efficiency of data processing and transfer.
Innovation Solution
The implementation of neural networks using matrices or arrays of resistors allows for direct analog voltage transfer between layers, omitting the need for ADCs and reducing chip area and power consumption by using resistor arrays and interface circuits to perform data transfer and processing without digital conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If ADCs are used between successive layers, then data conversion accuracy is improved, but chip area and power consumption increase
Solution Approach 1:
The patent removes ADCs from the neural network architecture between successive layers, extracting the digital conversion function entirely. Instead of converting analog signals to digital between layers, the system maintains analog signals throughout the network, using only simple interface circuits to transfer signals between resistor arrays representing different layers.
Solution Approach 2:
The patent introduces interface circuits as intermediaries between successive layers of resistor arrays. These interface circuits directly transfer analog signals without digital conversion, serving as a mediator that enables communication between layers while avoiding the area and power costs of ADCs.
2Measurement precision
If ADCs are used between successive layers, then data conversion accuracy is improved, but power consumption increases
Solution Approach 1:
The patent removes ADCs from the neural network architecture between successive layers, extracting the digital conversion function entirely. Instead of converting analog signals to digital between layers, the system maintains analog signals throughout the network, using only simple interface circuits to transfer signals between resistor arrays representing different layers.
Solution Approach 2:
The patent introduces interface circuits as intermediaries between successive layers of resistor arrays. These interface circuits directly transfer analog signals without digital conversion, serving as a mediator that enables communication between layers while avoiding the area and power costs of ADCs.
3Measurement precision
If ADCs are used between successive layers, then data processing accuracy is improved, but processing speed decreases
Solution Approach 1:
The patent removes ADCs from the neural network architecture between successive layers, extracting the digital conversion function entirely. Instead of converting analog signals to digital between layers, the system maintains analog signals throughout the network, using only simple interface circuits to transfer signals between resistor arrays representing different layers.
Solution Approach 2:
The patent introduces interface circuits as intermediaries between successive layers of resistor arrays. These interface circuits directly transfer analog signals without digital conversion, serving as a mediator that enables communication between layers while avoiding the area and power costs of ADCs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables faster processing, reduces chip area and power consumption, and improves the efficiency of data transfer between successive layers in neural networks, compared to traditional methods that rely on ADCs.
Implementation Method 1
The implementation of neural networks using matrices or arrays of resistors allows for direct analog voltage transfer between layers
Data Source
AI summary
An interface circuit includes an integrator circuit and a buffer circuit. The integrator circuit is configured to be electrically coupled to a column of memory cells, receive a signal corresponding to a sum of currents flowing through the memory cells of the column, and integrate the signal over time to generate an intermediate voltage. The buffer circuit is electrically coupled to an output of the integrator circuit to receive the intermediate voltage, and is configured to be electrically coupled to a row of further memory cells, generate an analog voltage corresponding to the intermediate voltage, and output the analog voltage to the further memory cells of the row.