Output Buffer Layout for Low-Capacitance DRAM Data I/O
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Solution Overview
Problem
Semiconductor devices, such as DRAM, face challenges in reducing capacitance at data I/O terminals to enhance data transfer rates and lower current consumption associated with data input/output operations.
Innovation Solution
The implementation of a data input/output circuit configuration that includes pull up and pull down output buffers with specific transistor arrangements and capacitor placement to minimize capacitance between the source and drain regions, reducing the overall capacitance added to the data I/O terminals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional output buffer configuration is used, then current consumption is reduced, but capacitance at data I/O terminal increases which limits data transfer rate
Solution Approach 1:
The output buffer is divided into multiple independent buffer units (first output buffer and second output buffer) that can operate independently. Each buffer unit has its own transistor pair and control logic, allowing the total capacitance to be distributed and reduced at any single data I/O terminal while maintaining overall buffering capacity through parallel operation.
2Productivity
If output buffer capacity is increased to handle more data, then data transfer capability improves, but capacitance at data I/O terminal increases which slows down transfer rate
Solution Approach 1:
The output buffer is segmented into multiple independent buffer units that can operate in parallel. This allows the system to handle increased data throughput by activating multiple segments simultaneously, while each individual segment maintains low capacitance at its data I/O terminal, thus preserving high transfer rates.
Solution Approach 2:
The output buffer employs dynamic control where different buffer units can be selectively activated based on data requirements. The control circuit dynamically selects which buffer unit to use, allowing the system to adapt buffer capacity to actual needs without permanently increasing capacitance at any single data I/O terminal.
Data Source
AI summary
Disclosed herein is an apparatus that includes a first wiring layer including first and second conductive patterns extending in a second direction and coupled to source and drain regions, respectively, and a second wiring layer including third and fourth conductive patterns extending in the second direction and coupled to the first and second conductive patterns, respectively. The first conductive pattern has first and second sections arranged in the second direction, and the second conductive pattern has third and fourth sections arranged in the second direction. The first and fourth sections are arranged in a first direction, and the second and third sections are arranged in the first direction. The third conductive pattern covers the first section without covering the second section. The fourth conductive pattern covers the third section without covering the fourth section.