Centrosymmetric Dual-Port SRAM Layout for Stable Read Currents
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Solution Overview
Problem
Existing dual-port SRAMs exhibit inconsistent read paths and reduced electrical performance due to asymmetric current paths and layout defects, leading to slower read speeds and variations in PMOS transistor performance.
Innovation Solution
The dual-port SRAM design improves symmetry by rearranging the layout of pass gates and transistors to create centrosymmetric subunits, increasing spaces between metal work function layers and active regions, which reduces impurity diffusion and enhances the stability of PMOS transistors, thereby improving read path symmetry and electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the existing dual-port SRAM layout is used with asymmetric current paths, then the device complexity is reduced, but the read path symmetry and electrical performance deteriorate
Solution Approach 1:
The patent applies asymmetry principle by intentionally designing symmetric layout structures (centrosymmetric subunits) to counteract the inherent asymmetry in conventional SRAM designs. By making the layout symmetric around a center point, the patent achieves symmetric current paths and improved read performance while maintaining manageable device complexity through this systematic approach to symmetry.
Solution Approach 2:
The patent divides the SRAM cell into multiple centrosymmetric subunits, each containing specific transistors and interconnections. This segmentation allows independent optimization of each subunit while ensuring overall symmetry, making the complex symmetric layout more manageable and implementable without excessively increasing device complexity.
2Area of stationary object
If the metal work function layers are placed closer to active regions, then the device area is reduced, but impurity diffusion increases and PMOS transistor performance stability deteriorates
Solution Approach 1:
The patent applies local quality principle by creating different spatial relationships between metal work function layers and active regions in different areas of the cell. Specifically, the symmetric layout ensures that certain regions have adequate spacing to prevent impurity diffusion, while other regions are optimized for area efficiency. This local differentiation allows the patent to maintain PMOS transistor performance stability in critical areas while minimizing overall cell area.
3Manufacturing precision
If the read paths are made symmetric, then the read current consistency is improved, but the layout complexity and manufacturing difficulty increase
Solution Approach 1:
The patent segments the SRAM cell into centrosymmetric subunits with standardized internal structures. Each subunit contains transistors and interconnections arranged in a consistent pattern that contributes to overall symmetry. This segmentation approach makes the symmetric layout more manufacturable by allowing standardized fabrication processes to be applied to each subunit, reducing the complexity of implementing read current consistency across the entire cell.
Solution Approach 2:
The patent uses copying principle by creating identical or mirror-image versions of transistor structures and interconnection patterns in symmetric positions. The centrosymmetric subunits are essentially copies or reflections of each other, ensuring consistent electrical characteristics and read current behavior. This copying approach simplifies manufacturing by using repeated patterns that can be fabricated with standard precision processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the symmetry of read paths and currents, stabilizes the electrical performance of PMOS transistors, and improves the overall stability and speed of read operations in dual-port SRAMs.
Implementation Method 1
increasing spaces between metal work function layers and active regions, which reduces impurity diffusion and enhances the stability of PMOS transistors
Data Source
AI summary
The present application discloses a dual-port SRAM having two ports. On a layout, pass gates connecting to the two ports are disposed near pull down transistors of corresponding memory nodes. A cell layout structure of the SRAM cell structure is centrosymmetric. In a first subunit layout structure, a pass gate and a first pull down transistor share the same active region, and an active region of the other pull down transistor is disposed between active regions of the first pull down transistor and a first pull up transistor. The present application improves the symmetry of read paths of the two memory nodes from two ports thus the symmetry of read currents, therefore the variation of the electrical performance of PMOS transistors is reduced and the stability of the electrical performance of the PMOS transistors is improved.