Quadrature Clock Correction Circuit for Duty Cycle and Phase Skew
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor memory devices face challenges in synchronizing clock signals due to internal time delays and duty cycle errors, which affect data transfer efficiency and accuracy.
Innovation Solution
A quadrature error correction circuit is implemented to concurrently adjust the skew and duty cycle errors of clock signals, using a duty cycle adjuster, phase splitters, multiplexers, and a phase detector to generate corrected clock signals with a 90-degree phase difference, ensuring accurate data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a clock signal is used for synchronization in a semiconductor memory device, then data transfer can be performed in a timed manner, but internal time delays and clock skew occur due to internal circuits
Solution Approach 1:
The patent implements a feedback mechanism where a phase detector continuously monitors the phase difference between clock signals and generates control signals to adjust delay elements, creating a closed-loop system that automatically compensates for clock skew and maintains synchronization accuracy
Solution Approach 2:
The patent applies preliminary action by pre-adjusting the phase of clock signals through controlled delay elements before they are used for data transfer operations, ensuring that timing relationships are established in advance to prevent synchronization errors
2Productivity
If clock signals are used for data transfer synchronization, then data transfer efficiency can be improved, but duty cycle errors occur affecting transfer accuracy
Solution Approach 1:
The phase detector continuously monitors duty cycle deviations and feeds back control signals to adjust the clock signal parameters, creating a self-correcting system that maintains precise duty cycle control during high-speed data transfer operations
Solution Approach 2:
The patent dynamically adjusts clock signal parameters including duty cycle and phase through controlled delay elements in response to detected errors, allowing the system to maintain precision while operating at high transfer rates
3Reliability
If internal circuits are added to compensate for time delay, then synchronization accuracy can be improved, but device complexity increases
Solution Approach 1:
The phase detector and delay control circuitry serve multiple functions including phase detection, duty cycle correction, and skew compensation, allowing a single circuit block to address multiple synchronization issues without proportionally increasing complexity
Solution Approach 2:
The patent introduces intermediate delay elements and control circuits that act as mediators between the clock signal source and the data transfer logic, isolating the complexity of synchronization correction from the main data path and enabling modular design
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A quadrature error correction circuit includes a duty cycle adjusting circuit, a phase interpolator, a phase detector, and a delay control circuit. The duty cycle adjusting circuit generates a first corrected clock signal and a second corrected clock signal whose skew and duty cycle error are concurrently adjusted by adjusting a delay of edges of a second clock signal and adjusting a delay of a falling edge of a first clock signal based on first through fourth control code sets. The phase interpolator generates a second delayed and selected clock signal by delaying a second selected clock signal selected from first through fourth adjusted clock signals. A phase detector detects a phase difference between a first selected clock signal and the second delayed and selected clock signal to generate an up/down signal. The delay control circuit generates the first through fourth control code sets based on the up/down signal.