Memory I/O Clock Gating for Independent Sub-Channel Operation
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Solution Overview
Problem
Existing memory systems for mobile communication devices require separate clock signals for each sub-channel, leading to increased power consumption and complexity in interface elements.
Innovation Solution
An input/output interface circuit that divides a common differential clock signal for each sub-channel, using a common receiving driver and sub-channels configured to receive and process the divided clock signals, along with chip select signals and command address signals, to independently operate each sub-channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate clock signals are provided for each sub-channel, then each sub-channel can operate independently, but power consumption increases and interface complexity increases
Solution Approach 1:
The patent merges the clock signal provision system by using a single common clock signal source that is shared across multiple sub-channels. Instead of providing separate clock signals for each sub-channel, the invention uses one common clock signal that can be selectively enabled for different sub-channels through chip select signals, thereby reducing the number of clock interface elements and power consumption while maintaining independent sub-channel operation capability.
Solution Approach 2:
The common clock signal serves multiple functions and multiple sub-channels simultaneously. A single clock signal line is designed to universally support clocking for any active sub-channel, making the clock interface multi-functional. This universal approach allows the same clock signal to be used across different sub-channels as needed, reducing redundancy and power consumption.
2Adaptability or versatility
If separate clock signals are provided for each sub-channel, then each sub-channel can operate independently, but device complexity increases
Solution Approach 1:
The patent merges multiple separate clock interface elements into a single common clock interface. Instead of having separate clock signal lines and associated interface circuitry for each sub-channel, the invention combines them into one shared clock signal path that can be selectively activated, thereby reducing interface complexity while preserving independent sub-channel functionality.
Solution Approach 2:
The common clock interface is designed to be universal, serving multiple sub-channels through a single interface structure. This multi-functional interface can be dynamically configured to provide clock signals to any active sub-channel, eliminating the need for multiple dedicated interfaces and reducing overall device complexity.
3Use of energy by stationary object
If a common clock signal is used for all sub-channels, then power consumption and complexity are reduced, but independent operation of sub-channels may be compromised
Solution Approach 1:
The patent introduces dynamic control mechanisms that allow the common clock signal to be selectively enabled or disabled for different sub-channels based on their operational state. Through dynamic chip select signals and logical AND operations, the system can activate the common clock signal for specific sub-channels only when needed, thereby maintaining independent sub-channel operation capability while using a shared clock resource.
Solution Approach 2:
The common clock signal provides continuous clocking capability to any active sub-channel without interruption. By maintaining the common clock signal as an always-on resource that can be selectively gated to different sub-channels, the system ensures continuous and reliable clocking for independent sub-channel operations while avoiding the power consumption of multiple separate clock signal generators.
Data Source
AI summary
An input/output interface circuit includes a common receiving driver configured to receive a differential clock signal and output a first clock signal corresponding to the differential clock signal and a pair of sub-channels connected to the common receiving driver. Each sub-channel of the pair of sub-channels may be configured to receive the first clock signal and a chip select signal, output a second clock signal through a logical AND operation of the first clock signal and the chip select signal, and output a single clock signal, among the second clock signal and one or more divided clock signals. The single clock signal is used to sample a command address signal.