Multi-DAC Output Synchronization Using Internal Delay Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for synchronizing digital/analog converters in high-frequency applications face challenges in aligning data due to propagation time differences and temperature tolerance issues, especially when working frequencies exceed 100 MHz, leading to signal degradation and complexity in clock management.
Innovation Solution
A method and device that synchronize analog data at the output of multiple digital/analog converters on the same active edge of a common reference clock by generating internal synchronization signals within each converter, using an external synchronization signal and clock signal, and applying delays to align data conversion on the slowest core, thereby ensuring synchronized data output on the same active edge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If propagation time alignment is achieved by adjusting track lengths, then data arrives simultaneously at all converters, but physical distance constraints make this difficult or impossible
Solution Approach 1:
The patent applies preliminary action by measuring propagation times in advance for each converter and pre-calculating the required delay values. The synchronization method determines the maximum propagation time beforehand and calculates compensation delays for all converters before operation begins, allowing the system to accommodate various physical layouts without requiring track length adjustments
Solution Approach 2:
The patent changes the parameter being controlled from physical track length to electronic delay time. Instead of adjusting the physical characteristics of signal paths, the invention introduces programmable delay parameters that can be configured software-defined, allowing synchronization to be achieved through parameter adjustment rather than physical modification
2Measurement precision
If synchronization pulse distribution is designed for precise propagation time compensation, then active clock edges match across converters, but evaluation becomes increasingly difficult above 100 MHz
Solution Approach 1:
The patent applies self-service by having each converter independently measure its own propagation time from the common reference clock to its internal timing circuitry. Each converter autonomously determines its delay characteristic and configures its own compensation, eliminating the need for complex external measurement and calculation systems
Solution Approach 2:
The patent uses feedback mechanisms where each converter monitors its own timing characteristics and adjusts its delay configuration based on measured propagation times. The system incorporates feedback loops that allow converters to automatically compensate for their individual timing variations, simplifying the overall synchronization implementation
3Manufacturing precision
If sampling clock is modified for synchronization, then converter alignment is achieved, but signal degradation occurs due to jitter
Solution Approach 1:
The patent segments the synchronization function from the sampling clock function. Instead of modifying the sampling clock itself, the invention introduces a separate synchronization mechanism using delay lines that operate independently, leaving the sampling clock unchanged and preserving signal quality while achieving converter alignment
4Manufacturing precision
If master/slave system with frequency subdivisions is used, then converter synchronization is achieved, but temperature tolerance is limited and clock management is complicated
Solution Approach 1:
The patent extracts the synchronization function from the complex master/slave clock management system. By separating synchronization from the hierarchical clock subdivision approach, the invention eliminates the need for multiple clock domains and complex phase relationships, simplifying clock management while maintaining synchronization accuracy and improving temperature tolerance
Data Source
AI summary
A method for synchronizing analog data (Data_ana1, Data_ana2) at the output of a plurality of digital/analog converters (DAC), comprising at least one conversion core (C1, C2), on an active edge of a common reference clock (Clk), the method comprising the following steps: a) supplying an external synchronization signal (SYNC_ext), to at least one converter, and supplying a signal of the common reference clock to the plurality of converters; b) generating, within each converter, an internal synchronization signal (SYNC_int), such that all the internal synchronization signals are aligned on an active edge of the common reference clock; c) for each of the converters, generating a start signal (START1, START2) which represents the start of the sending of digital data and counting a number of clock strokes until the internal synchronization signal is generated, and; d) applying a delay Ri (R1, R2) to each converter core, the delay being equal to the difference between the highest number counted in step c) and the number counted for the core. Device for implementing such a method.