Dual-DAC Phase Interpolator for Low-Distortion Memory Timing
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Solution Overview
Problem
Current mode phase interpolators in memory devices suffer from significant phase and amplitude errors during interpolation, leading to AM-to-PM distortion, which degrades the linear characteristics and timing accuracy, particularly at high clock frequencies.
Innovation Solution
A phase interpolator design incorporating a main DAC circuit and an auxiliary DAC circuit to adjust current output, using orthogonal phase inputs and weights, minimizing phase and amplitude errors through improved linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a current mode phase interpolator is used to avoid inter-power interference and frequency pulling, then frequency stability is improved, but phase and amplitude errors increase during interpolation
Solution Approach 1:
The phase interpolator is divided into multiple independent current mode phase interpolators, each handling a specific phase interpolation range. This segmentation allows each unit to operate with optimized parameters while maintaining overall frequency stability through modular architecture.
Solution Approach 2:
The invention dynamically adjusts operating parameters including bias currents, transistor sizes, and interpolation ratios based on the desired output phase and frequency. By changing these parameters adaptively, the system maintains frequency stability while minimizing phase and amplitude errors across different operating conditions.
2Device complexity
If a first-order linear code is used to adjust current output in a current mode phase interpolator, then circuit simplicity is maintained, but significant phase and amplitude errors occur during interpolation
Solution Approach 1:
The phase interpolator employs dynamic current adjustment mechanisms where bias currents and transistor operating points are continuously adapted based on the interpolation code. This dynamic operation enables higher precision phase and amplitude control while maintaining a relatively simple circuit topology through time-varying parameter optimization.
Solution Approach 2:
The system incorporates feedback mechanisms that monitor output phase and amplitude errors, then adjust internal current parameters accordingly. This feedback loop compensates for the limitations of first-order linear coding, achieving high precision interpolation without significantly increasing circuit complexity.
3Ease of operation
If amplitude errors are present in the CML level output, then AM-to-PM distortion occurs during conversion to CMOS level, but maintaining constant amplitude complicates the interpolation process
Solution Approach 1:
The phase interpolator performs preliminary amplitude normalization at the CML stage before conversion to CMOS level. By pre-adjusting the amplitude of differential signals to a standardized level prior to level conversion, the system eliminates the source of AM-to-PM distortion while keeping the interpolation process relatively simple through advance parameter standardization.
Solution Approach 2:
The invention introduces an intermediate amplitude control stage between the CML differential output and the CMOS level conversion. This intermediary component regulates the amplitude of signals before they undergo level conversion, preventing amplitude variations from being translated into phase distortions in the final output.
Data Source
AI summary
A phase interpolator providing a pair of differential outputs according to a plurality of inputs with a plurality of phases, the phase interpolator including: a main digital-to-analog converter (DAC) circuit configured to phase-interpolate a first input and a second input, which have orthogonal phases among the plurality of inputs, according to a main code to generate a main output signal; an auxiliary DAC circuit configured to phase-interpolate the first input and the second input according to an auxiliary code corresponding to the main code to generate an auxiliary output signal; and an output buffer configured to generate the pair of differential outputs according to a differential input based on a phase output signal, which is the sum of the main output signal and the auxiliary output signal.