Reception Clock Phase Shifting for Parallel Data Synchronization
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Solution Overview
Problem
Existing parallel data communication systems face challenges in maintaining reliable synchronization of data signals with clock signals, particularly in high-performance scenarios, leading to potential desynchronization issues.
Innovation Solution
A method and circuit for generating a data reception clock signal that is phase-shifted relative to the transmitted clock signal, utilizing an oscillating circuit, counter, and delay circuit to synchronize data signals by adjusting the phase of the clock signal based on the communication protocol used, ensuring synchronization at stable data points within the clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a plurality of communication channels are used to transmit data in parallel, then data transmission speed is improved, but synchronization reliability between data signals and clock signals deteriorates
Solution Approach 1:
The patent implements dynamic phase adjustment of the reception clock signal based on detected synchronization errors. The system continuously monitors the alignment between data signals and clock signals, and adjusts the phase of the reception clock signal in real-time to maintain optimal synchronization, thereby resolving the contradiction between high-speed parallel transmission and synchronization reliability.
Solution Approach 2:
The patent employs a feedback mechanism where the system detects synchronization status between incoming data signals and the reception clock signal, then uses this detection information to adjust the clock signal phase. This closed-loop feedback control ensures that synchronization reliability is maintained even at high data transmission speeds across multiple parallel channels.
2Reliability
If the phase of the clock signal is adjusted to achieve synchronization, then data transmission reliability is improved, but device complexity increases
Solution Approach 1:
The patent introduces a reception clock signal as an intermediary element that mediates between the transmitted clock signal and the data signals. This intermediary clock signal can be independently phase-adjusted without affecting the original transmitted clock, thereby achieving synchronization while minimizing additional circuit complexity.
Solution Approach 2:
The patent achieves synchronization by changing the phase parameter of the reception clock signal rather than modifying the fundamental clock frequency or data transmission parameters. This selective parameter adjustment allows for reliable synchronization with minimal impact on overall device complexity.
Data Source
AI summary
The present description concerns a method of generation of a first clock signal based on a second clock signal, the first and second clock signals having a same first period, and based on a third periodic signal having a second period equal to the first period divided by a number greater than or equal to two, the method comprising the following successive steps: counting a number of full periods of the third signal completed during a full period of the second clock signal; and generating the first clock signal by shifting the phase of the second clock signal by a delay equal to the second period multiplied by another number in the range from zero to the number.