Configuration Memory Latch With Resettable Read Path for FPGAs
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Solution Overview
Problem
Conventional programmable logic devices, such as FPGAs, face challenges in designing area-efficient configuration memory latches due to the use of SRAM cells, which are foundry and process dependent, and registers, which are not area-efficient, leading to difficulties in signal routing and stability when implementing complex functions on silicon platforms.
Innovation Solution
The implementation of a configuration memory latch circuit using a specific transistor network architecture, including pMOS and nMOS transistors, with input termination and a reset cycle mechanism, to facilitate area-efficient and readable storage elements in FPGAs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If SRAM cells are used as storage elements, then area efficiency is improved, but foundry and process dependency increases causing migration difficulties
Solution Approach 1:
The latch circuit is designed with standardized pMOS and nMOS transistor networks that can function across different foundries and fabrication processes. By using universal transistor-based latch structures with standardized control signals (reset, read, write), the design achieves portability and adaptability to various manufacturing processes while maintaining area efficiency, eliminating the foundry-specific dependency of SRAM cells.
2Ease of manufacture
If registers are used as storage elements, then standard cell library availability is improved, but area efficiency deteriorates
Solution Approach 1:
The invention uses simple transistor-based latch structures that are much more area-efficient than conventional registers. These latch circuits use basic pMOS and nMOS transistor networks with minimal transistor counts, effectively replacing complex register structures with simpler, area-efficient alternatives that still provide the necessary storage functionality for configuration memory in FPGAs.
3Area of moving object
If conventional latches are used as storage elements, then area efficiency is improved, but readability difficulties arise
Solution Approach 1:
The latch circuit incorporates dedicated read control mechanisms with control signals (such as read enable and word line read signals) that mediate between the stored data and the output. These control mechanisms enable selective reading of latch contents without disturbing the stored data, effectively solving the readability problem while maintaining the area efficiency of latch-based storage.
4Area of moving object
If latches are used as storage elements, then area efficiency and power consumption are improved, but data integrity during read/write operations must be maintained
Solution Approach 1:
The latch circuit employs preliminary reset cycles and controlled write operations that prepare the latch state before data is written or read. Reset control signals are applied in advance to ensure the latch is in a known state, and write operations are controlled through word line write signals that enable data to be written only when appropriate, preventing data corruption and maintaining integrity throughout read and write operations.
Data Source
AI summary
An area efficient input terminated readable and resettable configuration memory latch is disclosed. A pull-up network and a pair of pull-down networks operate to set the value of an internal node based, in part, on the state of the input terminated bit line and a word line write input. The internal node is inverted to form the output of the configuration memory latch. A reset line operates to reset the latch and a reset cycle is initiated prior to each write cycle. In some embodiments, the configuration memory latch includes a scan mode input, which, when asserted, facilitates automated testing of a programmable logic device that includes the configuration memory latch. Asserting the scan mode input enables Design for Test functionality. A sensing block is configured to sense the state of the bit when a word line read signal and a read enable signal are both asserted.