DDR PAM4 Feedback Circuit for Memory ISI Mitigation
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Solution Overview
Problem
Memory devices face challenges in reducing inter-symbol interference (ISI) in signals, particularly in multi-level signaling schemes like PAM4, which degrades signal integrity and complicates data detection.
Innovation Solution
Implementing a feedback circuit with DFE and DDR timing schemes in memory devices to mitigate ISI, using latch circuits with tunable reference voltages and parallel receivers for differential signaling, and incorporating multi-tap feedback circuits to correct inter-symbol interference across multiple sampling events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-level signaling (e.g., PAM4) is used to increase data transmission rate, then productivity is improved, but inter-symbol interference increases and signal integrity deteriorates
Solution Approach 1:
The patent implements a decision feedback equalizer (DFE) that uses feedback signals from previously detected symbols to compensate for inter-symbol interference in current symbol detection. The feedback circuit generates correction signals based on detected data and feeds them back to the differential amplifier, improving signal integrity while maintaining high-speed multi-level signaling.
Solution Approach 2:
The patent applies preliminary equalization by anticipating and compensating for inter-symbol interference before it fully degrades the signal. The DFE structure calculates expected interference from previous symbols and subtracts it in advance from the current signal, preventing detection errors.
2Reliability
If feedback circuits are added to reduce inter-symbol interference, then signal integrity is improved, but device complexity increases
Solution Approach 1:
The patent combines the feedback equalization function with the existing differential amplifier and latch circuit structures. The feedback signals are integrated into the differential amplification process, and the control logic is merged with the existing timing and decoding circuits, reducing overall system complexity while maintaining signal integrity improvements.
Data Source
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AI summary
Methods, systems, and devices for feedback for multi-level signaling in a memory device are described. The memory device may use pulse amplitude modulation (PAM) signaling (e.g., PAM4) that is synchronized with a clock signal using a double data rate (DDR) to communicate information with a host device. The memory device may include a first circuit for determining voltage levels of sampling events associated with a rising edge of the clock signal and a second circuit for determining voltage levels of sampling events associated with a falling edge of the clock signal. A feedback circuit may receive a feedback signal associated with the first circuit and modify the signal input into the second circuit. The feedback circuit may include a latch circuit configured to receive portions of the signal and receive a first control signal and a second control signal to tune portions of the signal.