Memory Clock Duty Training With Concurrent Read Offset Correction
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Solution Overview
Problem
Current semiconductor memory devices face challenges in reducing clock training time due to the sequential and resource-intensive process of adjusting duty cycles for data and read clocks, which is critical for accurate data access operations but consumes significant time and system resources.
Innovation Solution
A memory device with signal pins for receiving and transmitting clocks, performing duty cycle monitoring, and generating timing-adjusted clocks to calculate and correct duty errors, allowing simultaneous training of data and read clocks, thereby reducing training time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If data clock training and read clock training are performed sequentially, then each clock can be trained thoroughly, but the total training time is significantly extended
Solution Approach 1:
The patent merges data clock training and read clock training into a single concurrent operation. The memory device performs duty cycle monitoring and training for both clocks simultaneously by sharing common hardware resources (duty cycle monitor, trainer circuit) and executing training algorithms in parallel, thereby reducing total training time while maintaining the measurement precision required for accurate duty cycle adjustment
Solution Approach 2:
The patent enables continuous training action by overlapping the training processes. Instead of completing data clock training fully before starting read clock training, the system maintains continuous useful action by initiating read clock training during data clock training, ensuring that both clocks receive the necessary adjustment attention without idle waiting periods
2Loss of time
If duty cycle monitoring and adjustment is performed for both data clock and read clock simultaneously, then training time is reduced, but system resource consumption increases
Solution Approach 1:
The patent implements universal hardware resources that can serve multiple functions. The duty cycle monitor and trainer circuit are designed to handle both data clock and read clock training tasks using the same physical components. This multi-functionality allows concurrent training operations without proportionally increasing hardware resource consumption, as the same resources are dynamically allocated to different clock training tasks
3Reliability
If separate training processes are used for data clock and read clock, then each clock receives dedicated attention, but the training process becomes complex and time-consuming
Solution Approach 1:
The patent merges separate training processes into a unified concurrent training framework. By combining the training algorithms and control logic into a single integrated process that handles both clocks, the system reduces overall process complexity while maintaining reliability through shared verification and adjustment mechanisms
Data Source
AI summary
An apparatus includes a host and a memory device connected to the host through a bus. The bus is used to communicate a data clock controlling data write timing during a write operation executed by the memory device and a read clock controlling data read timing during a read operation executed by the memory device. The memory device performs first duty cycle monitoring that monitors a duty cycle of the data clock, generates a first result, and provides a timing-adjusted data clock, performs second duty cycle monitoring that monitors a duty cycle of the read clock, generates a second result, and provides a timing-adjusted read clock, calculates an offset of the read clock based on the timing-adjusted data clock, the result and the second result, and corrects a duty error of the read clock using a read clock offset code derived from the offset of the read clock.