Bit Line Sense Amplifier With Offset Cancellation for Low-Latency Sensing
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Solution Overview
Problem
The existing bit line sense amplifiers in semiconductor memory apparatuses face challenges in reducing access latency due to offset failures and increased sensing time, which limits overall system performance, as they struggle to amplify voltage differences within the required time and are affected by offset voltages and coupling noise.
Innovation Solution
A bit line sense amplifier design that includes a dual sensing margin structure with capacitors and offset cancellation units, which cancels offset voltages during the charge-sharing section without increasing sensing time, eliminating the need for a separate pre-charge circuit and enhancing sensing accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the sense amplifier uses a conventional structure to amplify voltage difference, then the sensing operation can be performed, but the offset voltage reverses the sign of voltage difference causing sensing fail
Solution Approach 1:
The patent applies preliminary action by performing offset cancellation before the main sensing operation. The sense amplifier includes offset cancellation units that actively compensate for offset voltage in advance, ensuring that the voltage difference sign is not reversed during sensing. This preliminary compensation improves sensing accuracy by eliminating the harmful offset effect before it can cause sensing failures.
2Speed
If the sense amplifier increases amplification speed to reduce latency, then the access latency decreases, but the sensing margin is reduced by coupling noise and offset voltage
Solution Approach 1:
The patent implements feedback mechanisms through offset cancellation units that continuously monitor and compensate for offset voltage during the sensing operation. This feedback approach maintains a sufficient sensing margin even at high amplification speeds by dynamically counteracting offset effects and coupling noise, allowing the sense amplifier to operate quickly while maintaining reliability.
3Reliability
If the sense amplifier includes offset cancellation function, then the offset fail is eliminated, but the sensing time increases
Solution Approach 1:
The patent merges the offset cancellation function with the main sensing operation by integrating offset cancellation units into the sensing amplifier structure. This allows offset cancellation and voltage difference amplification to occur simultaneously during the charge-sharing section, eliminating the need for separate offset cancellation time and preventing sensing time failure while maintaining high sensing yield.
4Quantity of substance
If the sense amplifier operates in open bit line structure, then the bit line capacitance is reduced, but the coupling noise increases reducing sensing margin
Solution Approach 1:
The patent converts the harmful effect of coupling noise into a beneficial outcome by using offset cancellation units that specifically target and compensate for noise-induced voltage shifts. The offset cancellation mechanism transforms the problematic coupling noise into a correctable signal component, allowing the open bit line structure to maintain low capacitance while achieving accurate sensing through active noise compensation.
Data Source
AI summary
A bit line sense amplifier includes: a first inverter having an input terminal connected to a first sensing node and an output terminal connected to a second inner bit line; a second inverter having an input terminal connected to a second sensing node and an output terminal connected to a first inner bit line; a first capacitor connected between the first sensing node and the first inner bit line; a second capacitor connected between the second sensing node and the second inner bit line; an isolation unit configured to cut off a connection between the first inner bit line and a second bit line; and an offset cancellation unit configured to connect the first sensing node to the second inner bit line, the first inner bit line to the first bit line, the second sensing node to the first inner bit line, and the second inner bit line to the second bit line.