Memory Read Clock Selection for Distortion-Resistant Data Latching
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Solution Overview
Problem
The distortion of clock signals in memory systems, particularly during duty cycle adjustments, leads to incorrect data latching and increased power consumption in Central Processing Units (CPUs).
Innovation Solution
A control apparatus connected with a memory, comprising a receiving circuit, clock circuit, selection circuit, and latch circuit, which generates and selects appropriate clock signals to ensure correct data latching and reduces power consumption by using internal clock signals when external signals are distorted.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory uses external read clock signal for data output, then the data transmission follows memory clock timing, but the clock signal becomes distorted during duty cycle adjustment causing incorrect data latching
Solution Approach 1:
The patent introduces an intermediary clock selection mechanism that mediates between the distorted external read clock signal and the internal clock signal. The selection circuit acts as a mediator to choose the appropriate clock source based on signal quality, preventing the distorted external clock from directly causing incorrect data latching while maintaining proper data transmission timing.
Solution Approach 2:
The patent changes the clock signal parameter (source selection) dynamically based on the duty cycle adjustment state. When the external clock signal is distorted during duty cycle adjustment, the system switches to using the internal clock signal instead, thereby maintaining reliable data latching despite the harmful external clock conditions.
2Reliability
If the CPU continuously monitors clock signal quality to ensure correct latching, then data accuracy improves, but system complexity and power consumption increase
Solution Approach 1:
The patent implements a self-service mechanism where the memory system automatically monitors its own clock signal quality and autonomously switches between clock sources without requiring external CPU intervention. The selection circuit self-adjusts based on detected signal conditions, reducing system complexity and power consumption while maintaining data latching accuracy.
3Reliability
If the system uses internal clock signal for data latching, then data latching accuracy improves under distorted external clock conditions, but power consumption increases due to additional clock circuitry
Solution Approach 1:
The patent implements a dynamic clock selection system that adaptively chooses between external and internal clock sources based on real-time signal quality assessment. The system dynamically switches to the internal clock signal only when the external clock is distorted during duty cycle adjustment, rather than continuously using the internal clock, thereby maintaining data latching correctness while minimizing unnecessary power consumption from additional clock circuitry.
Data Source
AI summary
A control apparatus includes: a receiving circuit, configured to receive a read clock signal from the memory, and output the read clock signal; a clock circuit, configured to generate a first internal clock signal; a selection circuit, configured to receive the read clock signal and the first internal clock signal, and output one of the read clock signal and the first internal clock signal as a target read clock signal; and a latch circuit, configured to receive the target read clock signal and a read data signal sent by the memory, and perform latch processing on the read data signal by using the target read clock signal.