Memory Read Clock Selection Under Duty Cycle Distortion
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Solution Overview
Problem
In electronic devices, the distortion of clock signals during duty cycle adjustment in memory leads to incorrect data retrieval by the CPU, causing failure in adjusting the duty cycle of the clock signal.
Innovation Solution
A memory with a clock processing circuit that includes a duty cycle circuit, first and second clock generation circuits, and a selector. The circuit adjusts the duty cycle of an external data clock signal, generates first and second read clock signals, and selects one as a target read clock signal to ensure accurate data retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the memory adjusts the duty cycle of the data clock signal to optimize timing, then the timing accuracy is improved, but the clock signal becomes distorted causing incorrect data retrieval
Solution Approach 1:
The patent segments the clock signal processing into two independent paths: a duty cycle adjustment path for timing optimization and a clean clock signal path for accurate data retrieval. The first clock generation circuit generates a first read clock signal from the adjusted internal clock signal, while the second clock generation circuit generates a second read clock signal directly from the original data clock signal without duty cycle adjustment, ensuring it remains undistorted and reliable for data latching.
Solution Approach 2:
The patent introduces a selector as an intermediary component that chooses between the first read clock signal (from the adjusted path) and the second read clock signal (from the clean path). This selector mediates between the conflicting requirements of timing optimization and signal integrity, routing the appropriate clock signal based on which path provides the best performance for the current operation.
Data Source
AI summary
A memory, a control apparatus, a clock processing method, and an electronic device are provided. A clock processing circuit in the memory includes: a duty cycle module, configured to adjust a duty cycle of a data clock signal to output an internal clock signal; a first clock generation module, configured to receive the internal clock signal, and output a first read clock signal based on the internal clock signal, the first read clock signal being a pulse signal; a second clock generation module, configured to generate and output a second read clock signal during existence of the first read clock signal, the second read clock signal having only one level state change edge; and a selection module, configured to receive the first read clock signal and the second read clock signal, and output the first read clock signal or the second read clock signal as a target read clock signal.