Adaptive Data Receiver Equalization for Lower Power and ISI Control
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Solution Overview
Problem
Current data receiving circuits face challenges in reducing power consumption while improving receiving performance, particularly in addressing intersymbol interference and signal quality issues due to increasing channel loss at higher signal transmission rates.
Innovation Solution
The proposed solution involves a data receiving circuit that utilizes a decision equalization enable module to process feedback signals and control a second amplification module. This module selectively receives signal pairs with larger differences in level value to reduce intersymbol interference, and when interference is not a concern, it fixes the signal pair reception to minimize power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a continuous equalization circuit (CTLE or DFE) is used to compensate channel loss, then the signal quality and receiving performance are improved, but the power consumption increases
Solution Approach 1:
The patent implements dynamic switching between different equalization modes (DFE and CTLE) based on channel conditions. The equalization circuit can adaptively change its operation state, transitioning between full equalization, partial equalization, and disabled states, thereby optimizing power consumption while maintaining signal quality when needed
Solution Approach 2:
The patent changes the equalization parameter (equalization depth) dynamically based on detected channel loss levels. When channel loss is severe, full equalization is applied; when channel loss is mild, equalization is reduced or disabled, thus adjusting the parameter to balance power consumption and signal quality
2Measurement precision
If equalization circuit always operates to reduce intersymbol interference, then the receiving accuracy is improved, but the power consumption increases
Solution Approach 1:
The patent implements periodic assessment of channel conditions and adaptively enables or disables equalization based on the assessed needs. Instead of continuous operation, the equalization circuit is activated periodically when intersymbol interference is detected and deactivated when channel conditions are good, reducing overall power consumption while maintaining receiving accuracy when necessary
3Use of energy by moving object
If the equalization circuit is disabled to reduce power consumption, then the power consumption decreases, but the ability to handle channel loss and intersymbol interference deteriorates
Solution Approach 1:
The patent employs feedback mechanisms where the receiver continuously monitors channel conditions and signal quality. Based on this feedback, the system adaptively adjusts the equalization circuit's operation, enabling it when channel loss is severe and disabling it when channel conditions are good, thus balancing power consumption and reliability
Data Source
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AI summary
Embodiments of the disclosure provide a data receiving circuit, a data receiving system and a storage apparatus. The data receiving circuit includes: a first amplification module, configured to receive a data signal, a first reference signal and a second reference signal, perform first comparison on the data signal and the first reference signal to output a first signal pair, and perform second comparison on the data signal and the second reference signal to output a second signal pair; a decision equalization enable module, configured to receive an enable signal and a feedback signal, and output a control signal, where the enable signal has a first level value period, a level value of the control signal varies with a level value of the feedback signal, the enable signal has a second level value period, and the level value of the control signal is a fixed value; and a second amplification module, configured to receive the first signal pair or the second signal pair based on the control signal, and output a first output signal and a second output signal. According to the embodiments of the disclosure, the power consumption of the data receiving circuit can be at least reduced while the receiving performance of the data receiving circuit is improved.