Word Line Delay Control in Memory Circuits Under Voltage Swing
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Solution Overview
Problem
The resistance of conductive lines in digital devices, such as memory macros, affects the operating voltages and overall performance of semiconductor integrated circuits as they become smaller and more complex, leading to issues in IC performance.
Innovation Solution
A memory circuit design that includes a word line driver circuit coupled to a control circuit, which utilizes an adjustable delay circuit to delay the word line clock signal without reducing its pulse width, allowing for a more flexible memory design by adjusting the delay based on voltage differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the conductive lines are made smaller to reduce IC size, then the IC becomes more compact, but the resistance of conductive lines increases affecting operating voltages and performance
Solution Approach 1:
The patent introduces adjustable delay circuits that modify the timing parameters of clock signals based on detected voltage levels. When voltage drops occur due to reduced conductive line dimensions, the delay circuit adjusts the clock signal timing to compensate, maintaining reliable operation despite the smaller IC size
2Reliability
If the word line clock signal is delayed to address voltage issues, then voltage-related performance is improved, but the pulse width may be reduced
Solution Approach 1:
The patent employs dynamically adjustable delay circuits that can adaptively modify the delay amount based on real-time voltage detection. This dynamic adjustment allows the system to optimize both the delay (for voltage compensation) and pulse width (for signal integrity) under different operating conditions, rather than using a fixed delay that would compromise pulse width
Solution Approach 2:
The delay circuit parameters are made adjustable to change the delay amount without proportionally reducing the pulse width. By independently controlling the delay parameter, the system can compensate for voltage issues while preserving adequate pulse width for reliable clock signal operation
3Reliability
If a fixed delay circuit is used to address voltage differences, then voltage compensation is achieved, but design flexibility is reduced
Solution Approach 1:
The patent implements dynamically adjustable delay circuits with control inputs that allow the delay amount to be modified based on different operating conditions, memory cell types, and voltage levels. This dynamic capability provides design flexibility while maintaining voltage compensation functionality
Solution Approach 2:
The adjustable delay circuit is designed to work with different memory cell types and voltage conditions, making it a universal solution that can be applied across various memory designs. The circuit can be configured for different delay amounts and can adapt to different operating scenarios, enhancing design versatility
Data Source
AI summary
A memory circuit includes a control circuit coupled to the word line driver circuit. The control circuit is configured to delay a leading or falling edge of a word line signal in response to at least a first clock signal. The control circuit includes a first clock circuit configured to generate a second clock signal in response to a first reset signal and a clock signal, and an adjustable delay circuit configured to adjust a delay between the second and third clock signal in response to the second clock signal and an enable signal. The third clock signal is a delayed version of the second clock signal. An amount of the delay between the second and third clock signal is based on a voltage difference between a first supply voltage having a first swing, and a second supply voltage having a second swing.