SRAM Supply Voltage Circuit Using Replica Latches for Data Retention
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Solution Overview
Problem
Existing SRAMs face challenges in reducing power consumption during low power modes due to variations in threshold voltages of FETs caused by temperature, age, and process variations, which require higher tolerance margins and thus higher power consumption.
Innovation Solution
A voltage generation circuit that includes two reference generation circuits, each with a replica SRAM latch, compares the threshold voltages of PFETs and NFETs to determine the higher voltage, which is then used to generate a supply voltage that is sufficient to retain data while minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a higher supply voltage is used to account for threshold voltage variations, then data retention reliability is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic voltage adjustment by switching between a first supply voltage (higher) and a second supply voltage (lower) based on operational mode. During active modes, the higher voltage ensures reliable data retention despite threshold variations. During low-power modes, the lower voltage reduces power consumption while still maintaining adequate retention, achieving adaptability between reliability and power efficiency.
Solution Approach 2:
The patent changes the supply voltage parameter dynamically based on operational requirements. By adjusting the voltage level according to whether the SRAM is in active or low-power mode, the system optimizes the trade-off between data retention reliability and power consumption, avoiding the need to maintain high voltage continuously.
2Reliability
If a fixed high supply voltage is used to ensure data retention across all conditions, then reliability is improved, but adaptability to different power modes deteriorates
Solution Approach 1:
The patent makes the supply voltage dynamic rather than fixed, allowing the system to adapt between different power modes. The voltage generation circuit responds to mode signals and adjusts the output voltage accordingly, enabling the SRAM to operate reliably in both active and low-power modes with appropriate voltage levels.
Solution Approach 2:
The patent segments the operational modes into distinct categories (active mode and low-power mode) with different voltage requirements. By separating the voltage generation for different modes and selecting the appropriate one based on operational state, the system achieves both reliability and adaptability to different power conditions.
3Reliability
If tolerance margins are increased to account for threshold voltage variations, then data retention is improved, but power consumption increases
Solution Approach 1:
The patent dynamically adjusts the supply voltage to match actual operational needs rather than maintaining a fixed high voltage with large tolerance margins. During low-power modes, the reduced voltage minimizes energy loss while still providing sufficient margin for data retention under varying threshold conditions, optimizing the balance between reliability and energy efficiency.
Data Source
AI summary
A memory includes a supply voltage generation circuit for providing a supply voltage to a plurality of SRAM cells of the memory during at least one mode of memory operation. The supply voltage generation circuit includes a first reference generation circuit that includes at least one SRAM cell with a replica SRAM latch. The first reference generation circuit provides a first voltage during an at least one mode of memory operation. The supply voltage generation circuit includes a second reference generation circuit that includes at least one SRAM cell with a replica SRAM latch. The second reference generation circuit provides a second voltage during the at least one mode of memory operation. The voltage generation circuit includes an output for providing a supply voltage to the plurality of cells during the at least one mode of memory operation.


