RRAM-Integrated nvSRAM Cell Layout for Fast Low-Power Retention
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Solution Overview
Problem
Conventional non-volatile static random access memory (nvSRAM) solutions fail to achieve high-speed access, low operation voltage, and low power consumption simultaneously while maintaining non-volatile storage capabilities.
Innovation Solution
Incorporating resistive random-access memories (RRAMs) between SRAM storage nodes and transistors, specifically between the drains of pull-up and pull-down transistors, to enable non-volatile storage without increasing the layout area, utilizing a 6T4C architecture with RRAMs positioned for setting contacts and overlapping with transistor drains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If data is transferred to other non-volatile memory (flash, MRAM, PCM) before power cut-off, then non-volatile storage capability is achieved, but high-speed access, low operation voltage and low power consumption cannot be simultaneously achieved
Solution Approach 1:
The patent merges SRAM circuit structure with RRAM memory elements by integrating RRAM cells at the drain nodes of the SRAM cross-coupled inverters. This combination allows the memory to simultaneously achieve non-volatile storage (through RRAM) and maintain SRAM's high-speed access characteristics, eliminating the need to transfer data to external non-volatile memory devices.
Solution Approach 2:
The integrated RRAM-SRAM structure serves multiple functions: the RRAM elements provide non-volatile data retention while the SRAM circuit provides high-speed read/write operations. This multi-functional design allows the same memory cell to deliver both volatile and non-volatile memory characteristics without requiring separate memory devices.
2Area of stationary object
If RRAMs are set between SRAM storage nodes and transistors, then non-volatile storage is achieved without increasing layout area, but device complexity increases
Solution Approach 1:
The RRAM memory elements are nested within the existing SRAM circuit structure by placing them at the drain nodes of the cross-coupled inverters. This nesting approach allows the RRAM cells to be integrated into the SRAM layout without requiring additional area, as the RRAM elements share the same physical space and interconnect structure as the SRAM transistors.
Solution Approach 2:
The patent introduces RRAM elements as intermediary components between the SRAM storage nodes and the pull-up/pull-down transistors. These RRAM intermediaries enable non-volatile data retention by maintaining their resistive state, while the SRAM circuit continues to provide high-speed access through its traditional read/write mechanisms.
3Duration of action of stationary object
If conventional nvSRAM approaches are used, then non-volatile storage is achieved, but power consumption increases
Solution Approach 1:
The RRAM elements provide self-service non-volatile data retention through their inherent resistive switching characteristics. Once data is written to the RRAM cells, they maintain their resistance state without requiring continuous power supply or periodic refresh operations, thereby significantly reducing power consumption compared to conventional DRAM-based approaches.
Solution Approach 2:
The patent utilizes the resistive state parameter of RRAM materials to encode and retain data. By switching between high-resistance and low-resistance states, the RRAM cells can store data non-volitally without requiring continuous energy input, thereby reducing the power consumption associated with data retention.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves competitive advantages of high-speed access, low operation voltage, and low power consumption while ensuring non-volatile storage, enhancing the robustness and efficiency of memory operations.
Implementation Method 1
resistive random-access memory (RRAM)
Data Source
AI summary
An non-volatile static random access memory (nvSRAM) is provided in the present invention, including a first pass gate transistor, a second pass gate transistor, a first pull-up transistor, a second pull-up transistor, a first pull-down transistor and a second pull-down transistor, which construct collectively two cross-coupled inverters with two storage nodes, wherein resistive random-access memories (RRAM) are set between the first storage node, the first pull-up transistor and the first pull-down transistor and between the second storage node, the second pull-up transistor and the second pull-down transistor.