Write Training Circuit for Data-Strobe Skew Alignment
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Solution Overview
Problem
Semiconductor devices face increasing challenges in maintaining timing synchronization between data signals and data strobe signals due to skew, which affects operational reliability, especially as device speeds increase, and existing write training operations have limitations in correcting random skew and meeting time specifications.
Innovation Solution
A semiconductor device and method that perform a write training operation by sequentially adjusting delay values of input paths of data signals based on the delay value of the data strobe signal, allowing for automatic operation before ZQ calibration, using a data input circuit, delay circuit, data alignment circuit, code generation circuit, and lock-detection circuit to align and stabilize signal timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the operating speed of the semiconductor device is increased, then the productivity is improved, but the timing skew between data strobe signal and data increases, worsening the reliability
Solution Approach 1:
The patent performs a write training operation before normal operation to pre-adjust the delay values of data paths. This preliminary action compensates for timing skew before high-speed operation begins, allowing the device to maintain timing synchronization even at increased operating speeds. The delay values are trained and stored in advance, so when the device operates at high speed, the timing skew is already corrected.
2Reliability
If a write training operation is performed to correct timing skew, then the reliability is improved, but the operation time increases, worsening the productivity
Solution Approach 1:
The patent changes the delay parameter of data paths during the write training operation. By adjusting the delay values of multiple data paths and evaluating timing margins, the system finds optimal delay settings that correct timing skew. This parameter adjustment allows the device to achieve reliable timing synchronization at high operating speeds while minimizing the training time required.
Solution Approach 2:
The write training operation is performed once during initialization or power-up, and the resulting delay values are stored for reuse. This preliminary action eliminates the need for repeated training operations, so the time loss occurs only once while enabling sustained high-speed operation thereafter.
3Reliability
If delay values of data paths are adjusted to meet time specifications, then the reliability is improved, but the device complexity increases due to additional training circuits
Solution Approach 1:
The patent divides the data path into multiple segments, each with independently adjustable delay elements. By segmenting the data path and adjusting delay values at different stages, the system can precisely control timing for each data line. This segmentation allows reliable timing specification compliance while keeping each individual delay adjustment simple and modular.
Data Source
AI summary
A semiconductor device includes a data input circuit suitable for receiving a training clock to provide first data signals and a strobe signal according to a plurality of input control signals in a training mode; a delay circuit suitable for outputting second data signals by delaying the first data signals according to delay values corresponding to respective setting codes; a data alignment circuit suitable for outputting third data signals by aligning the second data signals according to the strobe signal; a code generation circuit suitable for generating a preliminary code corresponding to the third data signals according to the training clock, and sequentially storing the preliminary code as the setting codes according to a code-lock signal; and a lock-detection circuit suitable for activating the code-lock signal based on the training clock and the preliminary code.