Folded DFE Comparator for Low-Voltage Serial Link ISI Reduction
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Solution Overview
Problem
Existing decision feedback equalizers face challenges in reducing intersymbol interference (ISI) in serial links due to non-idealities, requiring complex circuits and higher supply voltages, which limits their suitability for low-voltage applications.
Innovation Solution
A comparator with a folded topology and decision feedback equalization is introduced, featuring a regeneration stage with cross-coupled inverters and switching transistors that enable efficient ISI reduction using compare voltages adjusted based on previous bit values, reducing the number of stacked transistors and allowing operation at lower supply voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional decision feedback equalizers are used to reduce intersymbol interference, then ISI reduction is achieved, but the circuit complexity increases and higher supply voltages are required
Solution Approach 1:
The equalizer circuit is segmented into distinct functional blocks: a first comparator for comparing the received signal with a reference voltage, a second comparator for comparing with an equalized signal, and a combiner for merging the comparison results. This segmentation allows each block to perform a specific function with simpler circuitry, reducing overall complexity while maintaining effective ISI reduction capability.
Solution Approach 2:
An intermediate equalized signal is introduced as a mediator between the received signal and the final decision. The second comparator processes this intermediate signal to generate correction information that compensates for ISI effects. This intermediary approach enables gradual signal refinement without requiring complex direct processing of the original distorted signal.
2Reliability
If traditional decision feedback equalizers are used to reduce intersymbol interference, then ISI reduction is achieved, but the supply voltage requirement increases
Solution Approach 1:
The equalization function is segmented across multiple comparators operating at lower individual voltage levels. Each comparator processes a specific aspect of the signal (received signal vs. reference, equalized signal vs. reference) and combines their outputs. This segmentation allows the system to achieve the required signal-to-noise ratio and ISI reduction at lower supply voltages compared to a single high-voltage comparator approach.
Solution Approach 2:
The comparison results from multiple low-voltage comparators are merged in the combiner to produce the final equalized output. This merging of multiple lower-voltage processing paths achieves the same or better performance than a single high-voltage path, thereby reducing the overall supply voltage requirement while maintaining effective ISI reduction.
3Reliability
If complex circuits are used in decision feedback equalizers, then better ISI reduction is achieved, but the number of stacked transistors increases
Solution Approach 1:
The transistor stacking is segmented by distributing the equalization function across multiple comparators, each with a limited number of stacked transistors. Instead of one deep stack handling all equalization functions, each comparator has a shallow stack performing a specific comparison task. This segmentation reduces the maximum transistor stack depth while achieving the same overall equalization performance through coordinated operation of multiple comparators.
Data Source
AI summary
In certain aspects, a comparator includes an input stage and a regeneration stage. The input stage includes a first input circuit coupled to a first node and a second node, a first switching transistor configured to enable the first input circuit if a previous bit value is one, a second input circuit coupled to the first node and the second node, and a second switching transistor configured to enable the second input circuit if the previous bit value is zero. The regeneration stage includes a first inverter, a second inverter cross coupled with the first inverter, a first drive transistor coupled to the first inverter, wherein a gate of the first drive transistor is coupled to the second node, and a second drive transistor coupled to the second inverter, wherein a gate of the second drive transistor is coupled to the first node.