Memory Bank Delay Circuit for Asynchronous Signal Timing Calibration
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Solution Overview
Problem
In semiconductor memory devices, asynchronous signals and command signals often experience timing variations due to propagation delays, affecting the accuracy of internal test results across memory banks located at different physical locations within a memory chip.
Innovation Solution
A delay circuit is implemented within the memory device to calibrate the asynchronous signal, ensuring a common timing relationship with the command signal across all memory banks, thereby improving testing accuracy by synchronizing the asynchronous signal with the clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a single shared route is used to route asynchronous signals to all memory banks, then physical space is saved, but timing variations occur due to propagation delays
Solution Approach 1:
The patent divides the single shared asynchronous signal route into multiple independent routed signals, each dedicated to a specific memory bank. This segmentation allows each signal to have its own optimized routing path, eliminating timing variations caused by shared route propagation delays while maintaining space efficiency through systematic routing organization.
Solution Approach 2:
The patent implements bank-specific routed signals that are locally optimized for each memory bank's physical location. Each memory bank receives a dedicated asynchronous signal routed specifically to it, allowing timing calibration tailored to each bank's position. This local quality approach ensures that signals arriving at different banks experience consistent timing relationships with their respective command signals.
2Manufacturing precision
If independent command signals are sent to each memory bank, then timing control is improved, but timing variations occur due to different propagation distances
Solution Approach 1:
The patent introduces a timing calibration process that performs preliminary adjustment of asynchronous signal timing for each memory bank before actual operations. By pre-calibrating the timing relationship between asynchronous signals and command signals for each bank, the system compensates for propagation delay variations, ensuring synchronized timing across all banks without requiring additional time delays during operation.
3Measurement precision
If timing calibration is performed for each memory bank, then testing accuracy is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal timing calibration mechanism that can be applied to all memory banks through a standardized process. The same calibration methodology and signal routing structure are used across every bank, allowing the system to achieve precise timing calibration for each bank while maintaining overall system simplicity through reuse of the same calibration framework and routing patterns.
Data Source
AI summary
A delay circuit is coupled to a memory device. At least a portion of the delay circuit is disposed in one or more memory banks on one or more memory chips of the memory device. The delay circuit is configured to calibrate an asynchronous signal received at each of the one or more memory banks so that the calibrated asynchronous signal has a common timing relationship with a respective internal command signal received at the corresponding memory bank for all of the one or more memory banks on the memory device. The calibrated asynchronous signals are used in various internal test operations to improve testing accuracy.