DIMM Error Protection Using Interleaved Multibit Symbols
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Solution Overview
Problem
Existing chipkill schemes for memory devices, such as DIMMs, fail to provide adequate error protection and performance efficiency, especially when operating with 16-bit wide data buses, leading to increased latency and decreased error correction capabilities.
Innovation Solution
The implementation of an error correction and detection scheme using interleaved multibit symbols across multiple memory devices, which generates and encodes data into codewords that are distributed across different memory locations, allowing for independent error correction and detection within each codeword, thereby enhancing protection and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If existing chipkill schemes are applied to 16-bit wide data bus DIMMs, then memory capacity and bandwidth are increased, but error protection capability and performance efficiency deteriorate
Solution Approach 1:
The data bus is segmented into multiple lanes (e.g., four 4-bit lanes) and error correction codes are independently applied to each lane. This segmentation allows the system to maintain high capacity through parallel processing while preserving error protection capability by treating each lane as an independent error correction unit, resolving the contradiction between increased memory capacity and maintained reliability.
2Productivity
If existing chipkill schemes are applied to 16-bit wide data bus DIMMs, then memory bandwidth is increased, but latency increases and performance efficiency decreases
Solution Approach 1:
By dividing the 16-bit data bus into multiple independent lanes with separate error correction code operations, the system can process multiple lanes in parallel. This parallel processing approach maintains high bandwidth while reducing latency compared to sequential processing of the entire 16-bit bus, as error correction can occur simultaneously across all lanes rather than waiting for complete bus transactions.
3Quantity of substance
If wider data bus memory chips are used, then memory capacity and bandwidth are improved, but error correction capability decreases
Solution Approach 1:
The wide data bus is divided into multiple narrower lanes, each with its own simplified error correction code operation. This approach maintains error correction capability by applying proven ECC algorithms to each lane independently, avoiding the need to redesign complex error correction for the entire wide bus, thus reducing overall system complexity while preserving capacity.
Solution Approach 2:
The lane-based error correction approach provides a universal solution that can be applied to various bus widths (e.g., 4-bit, 8-bit, 16-bit, 32-bit) by simply adjusting the number of lanes. This multi-functional approach allows the same error correction mechanism to serve different memory configurations, reducing the need for specialized complex error correction designs for each bus width.
Data Source
AI summary
Symbols interleaved among a set of codewords can provide an error correction/detection capability to a dual in-line memory module (DIMM) with memory chips having a comparatively larger bus width. Data corresponding to a set of multibit symbols and received from one or more memory devices can be interleaved/distributed with other bits of at least one codeword.