Multiphase Clock Skew Correction in Memory Delay Circuits
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Solution Overview
Problem
Existing memory systems using multiphase clock signals face performance deterioration due to timing errors or skew between clock signals, which affect signal quality and speed.
Innovation Solution
A memory device and system that includes a DC conversion circuit to convert edge-triggered phase signals into DC voltages, a comparator to compare these voltages, and a control logic to generate delay codes for correcting skew errors, utilizing low-pass filters and level shifters to ensure accurate phase spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiphase clock signals are used for high-speed data operations, then data transmission speed is improved, but timing skew errors between clock signals deteriorate signal quality
Solution Approach 1:
The patent applies preliminary action by detecting phase spacing errors before they cause significant signal degradation. The error detection circuit continuously monitors the spacing between multiphase clock signals and generates correction signals in advance to adjust timing skew, preventing signal quality deterioration while maintaining high-speed operation
Solution Approach 2:
The patent implements feedback through a closed-loop system where the error detection circuit monitors phase spacing, generates correction signals based on detected errors, and feeds these corrections back to delay circuits that adjust the timing of clock signals. This continuous feedback mechanism dynamically maintains signal quality during high-speed data transmission
2Reliability
If clock signal timing is adjusted to correct skew errors, then signal quality is improved, but device complexity increases due to additional correction circuits
Solution Approach 1:
The patent applies segmentation by dividing the clock signal correction function into separate modular components: error detection circuits for each phase comparison, individual delay circuits for each clock signal, and a central control logic. This modular segmentation allows independent optimization and maintenance of each component while managing overall system complexity
Solution Approach 2:
The patent implements universality through a multiplexer that sequentially selects and processes error signals from multiple phase comparisons using a single comparator circuit. This multi-functionality allows one comparator to serve multiple phase spacing detection tasks, reducing the total number of comparators needed and simplifying the overall circuit architecture
3Measurement precision
If phase spacing errors are detected and corrected, then data operation accuracy is improved, but processing time is increased due to error detection and correction steps
Solution Approach 1:
The patent applies continuity of useful action by implementing continuous error detection and correction rather than periodic adjustments. The error detection circuits continuously monitor phase spacing, and the feedback mechanism continuously generates and applies correction signals, ensuring that timing accuracy is maintained without interruption throughout high-speed data operations
Solution Approach 2:
The patent implements skipping by using parallel error detection paths that simultaneously evaluate multiple phase spacing relationships. This allows the system to rapidly identify and correct the most critical timing skew errors without sequentially processing all possible phase combinations, thereby reducing the effective correction time
Data Source
AI summary
A memory device includes a DC conversion circuit that receives a first edge-triggered phase signal having first pulses each extending from a rising edge of a first phase signal of a multiphase clock to a later rising edge of a second phase signal of the multiphase clock and a second edge-triggered phase signal having second pulses each extending from a rising edge of the second phase signal to a later rising edge of the first phase signal, and outputting a first voltage corresponding to the first edge-triggered phase signal and a second voltage corresponding to the second edge-triggered phase signal, a comparator that compares the first voltage with the second voltage, control logic that generates a control code corresponding to an output value from the comparator, and a delay cell that delays the second phase signal according to the control code.