Memory Data Merger and Aligner Layout for Skewed Read Timing
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Solution Overview
Problem
In semiconductor devices with both memory and non-memory on a single chip, increasing the size of the memory cell array leads to signal delay skew between distant and near memory cells, complicating design and requiring additional compensation to manage data latency and area reduction.
Innovation Solution
A memory device with a memory cell array connected to word and bit lines in a matrix form, featuring multiple mergers to transform data into direct current and pulse forms, and an aligner to synchronize data output edges with control pulses, reducing data register stages and managing skew through edge delay units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the size of the memory cell array is increased to reduce memory region area and power consumption, then the area occupied by the memory region decreases and current consumption is reduced, but signal delay skew between distant and near memory cells increases, complicating design and requiring additional compensation devices
Solution Approach 1:
The memory cell array is divided into multiple banks, with each bank independently managed by its own data register. This segmentation allows each register to handle a smaller subset of cells, reducing the maximum distance between any cell and its corresponding register, thereby minimizing signal delay skew while maintaining overall large memory capacity.
Solution Approach 2:
The patent introduces a bank selection dimension to the memory architecture. Instead of a single linear array, the memory is organized in a two-dimensional structure with banks and cells within banks. This dimensional change allows parallel access paths through multiple banks, reducing the effective distance data must travel within each bank and compensating for skew.
2Area of stationary object
If the size of the memory cell array is increased to reduce memory region area, then integration is improved, but data latency increases due to more stages of data register arrays required
Solution Approach 1:
By segmenting the memory into multiple banks each with its own data register, the patent eliminates the need for multiple sequential stages of a single large data register array. Data can be accessed in a single stage within each bank, reducing latency while achieving the area reduction goal through efficient bank organization.
Solution Approach 2:
The data registers are pre-positioned at strategic locations within each bank, closer to the memory cells they serve. This preliminary placement of buffering elements reduces the distance data must travel and minimizes the number of clock stages required, thereby reducing latency before data reaches the output.
3Reliability
If additional devices are added to compensate for signal delay skew, then skew management is improved, but device complexity increases
Solution Approach 1:
The patent combines the skew compensation function with the existing data register structure. Rather than adding separate compensation devices, the data registers are designed to naturally handle skew through their placement and timing characteristics, merging multiple functions into a single integrated component and reducing overall device complexity.
Solution Approach 2:
The segmented bank structure allows each bank to self-manage its own timing and skew characteristics independently. Each data register automatically compensates for skew within its own bank without requiring external control or additional compensation circuitry, making the system self-sufficient and reducing complexity.
Data Source
AI summary
A memory device may comprise: a memory cell array in which memory cells are connected in matrix form to word lines and bit lines; a plurality of mergers connected in series to transfer data that is read from a selected memory cell among the memory cells included in the memory cell array and is transformed into one of a direct current form or a pulse form; and an aligner that synchronizes an edge of first output data, output by one of the plurality of mergers, with an edge of a control pulse, thereby delaying the edge of the first output data.