Memory Clock Buffer PLL Mode Switching for Lower Power
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Solution Overview
Problem
Current DDR memory topologies face challenges in managing clock scaling, leading to issues like additive jitter, clock skew, and margin constraints, especially at high transfer rates like 5600 Mbps. This results in increased power consumption by clock buffer devices, which can reduce battery life in portable systems and increase thermal loads in enterprise systems.
Innovation Solution
The proposed solution involves a clock buffer device with a phase-locked loop (PLL) mode selection mechanism. Based on the memory module's operating speed and the information handling system's topology, the clock buffer can switch between bypass mode, single-PLL mode, and dual-PLL mode to optimize power usage. In bypass mode, PLLs are disabled to reduce power consumption when operating at lower speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If dual-PLL mode is used to support high transfer rates (5600 Mbps), then memory module speed is improved, but power consumption increases
Solution Approach 1:
The clock buffer device dynamically switches between operational modes (bypass mode, single-PLL mode, dual-PLL mode) based on the required transfer rate. This dynamic adaptation allows the system to use only the necessary PLL resources for the current operating speed, reducing power consumption when full dual-PLL capability is not needed.
Solution Approach 2:
The system changes operational parameters (PLL enablement status) based on the transfer rate requirement. By adjusting which PLLs are active according to the speed needs, the system optimizes the balance between performance and power consumption across different operating conditions.
2Speed
If dual-PLL mode is enabled for clock scaling, then high-speed operation is achieved, but thermal load increases
Solution Approach 1:
The system dynamically adjusts the thermal footprint by enabling or disabling PLLs based on operational requirements. When high-speed operation is not needed, the system transitions to lower-power modes, thereby reducing thermal generation and managing heat dissipation more effectively.
3Speed
If clock buffer operates in dual-PLL mode continuously, then maximum performance is maintained, but battery life decreases
Solution Approach 1:
The system periodically assesses operational requirements and transitions between power modes accordingly. By switching to bypass mode or single-PLL mode during periods when maximum performance is not required, the system extends battery life while maintaining peak performance capability when needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces power consumption by up to 40 mW in bypass mode and achieves power savings of up to 20 mW in single-PLL mode, thereby extending battery life and reducing thermal loads in information handling systems.
Implementation Method 1
a first clock input coupled to an input of a first phase-locked loop (PLL), and a second clock input coupled to an input of a second PLL
Data Source
AI summary
A clock buffer device for a memory module includes a first clock input coupled to an input of a first phase-locked loop (PLL), and a second clock input coupled to an input of a second PLL. An output of the first PLL is selectably coupled to clock output buffers, and an output of the second PLL is selectably coupled to a subset of the clock output buffers. The clock buffer device receives a first indication that a first information handling system is configured to provide a first clock signal on the first clock input but to not provide a second clock signal on the second clock input, and, in response to the indication, couples the output of the first PLL to the clock output buffers and to disables the second PLL.