Shared Clock I/O Interface for Independent Memory Sub-Channels
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Solution Overview
Problem
Existing memory systems in mobile communication devices require separate clock signals for each sub-channel, leading to increased power consumption due to the need for multiple interface elements for clock signal transmission and reception.
Innovation Solution
An input/output interface circuit that utilizes a common receiving driver to receive a differential clock signal and output a first clock signal, which is then divided and distributed to each sub-channel for independent operation, allowing each sub-channel to receive a single clock signal generated through logical AND operations with chip select signals, and sample command address signals using this single clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate clock signals are provided for each sub-channel, then each sub-channel can operate independently, but power consumption increases due to multiple interface elements for clock signal transmission and reception
Solution Approach 1:
The patent merges the clock signal interface by providing a single common clock signal to multiple sub-channels instead of having separate clock signals for each sub-channel. This reduces the number of interface elements and lowers power consumption while maintaining independent sub-channel operation through individual chip select signals that gate the shared clock signal for each sub-channel.
Solution Approach 2:
The common clock signal serves multiple functions by being shared across multiple sub-channels. A single clock interface element performs the work of multiple separate interface elements, achieving universality where one clock signal path supports multiple independent sub-channels through selective activation using chip select signals.
2Use of energy by moving object
If a common clock signal is shared among multiple sub-channels, then power consumption is reduced, but device complexity increases due to the need for clock signal distribution and selection mechanisms
Solution Approach 1:
The patent segments the clock signal distribution by using individual chip select signals for each sub-channel to gate the common clock signal. This segmentation allows independent control of clock signal delivery to each sub-channel without requiring complex centralized distribution logic, simplifying the overall system while maintaining low power consumption.
Solution Approach 2:
The chip select signal acts as an intermediary between the common clock signal and individual sub-channels. This intermediary mechanism enables simple, independent control of clock signal delivery to each sub-channel without requiring complex distribution networks, reducing both power consumption and device complexity.
Data Source
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AI summary
An input/output interface circuit includes a common receiving driver configured to receive a differential clock signal and output a first clock signal corresponding to the differential clock signal and a pair of sub-channels connected to the common receiving driver. Each sub-channel of the pair of sub-channels may be configured to receive the first clock signal and a chip select signal, output a second clock signal through a logical AND operation of the first clock signal and the chip select signal, and output a single clock signal, among the second clock signal and one or more divided clock signals. The single clock signal is used to sample a command address signal.