Edge-Delay Memory Unit for Low-Power CIM MAC Readout
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Solution Overview
Problem
Computing-In-Memory (CIM) applications face challenges in reducing power consumption and improving accuracy due to restricted signal margins caused by power supply voltage VDD and high power consumption in readout circuits, which limits the performance of MAC operations.
Innovation Solution
A memory unit with time domain edge delay accumulation is controlled by a first and second word line, incorporating edge-delay cells and multiplexors that generate an edge-output signal with a delay time correlated to the multi-bit analog input voltage and weight, effectively improving signal margin and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple word lines are turned on simultaneously to increase bandwidth and reduce power consumption, then computing throughput is improved, but signal margin is restricted causing serious sensing errors
Solution Approach 1:
The patent transforms the output parameter from voltage domain to time domain. Instead of reading analog voltage values directly, the system converts MAC results into time-domain edge delay signals. This parameter transformation allows multiple word lines to operate simultaneously without signal margin restrictions, as the time-domain representation preserves computation accuracy while enabling parallel operations.
Solution Approach 2:
The patent replaces the traditional voltage-based analog-to-digital conversion mechanism with a time-domain edge delay accumulation mechanism. By substituting voltage signal processing with time-domain signal processing, the system eliminates the fundamental limitation of signal margin while maintaining computing accuracy through edge delay measurement.
2Power
If traditional readout circuits are used for MAC operations, then computing functionality is achieved, but power consumption is high
Solution Approach 1:
The patent extracts the readout function from traditional high-power voltage-based circuits and implements it using simple time-domain edge delay cells. By separating the computation function (performed by memory cells) from the readout function (performed by edge-delay cells), the system eliminates the need for complex, power-hungry analog-to-digital conversion circuits while preserving full computing functionality.
Solution Approach 2:
The patent employs simple edge-delay cells with basic transistors and capacitors instead of complex readout circuits. These simplified components consume significantly less power while achieving the same computational output through time-domain representation, effectively replacing expensive, power-intensive circuitry with cheaper, low-power alternatives.
3Measurement precision
If complex readout circuits are used to improve sensing accuracy, then measurement precision is improved, but device complexity and area increase
Solution Approach 1:
The patent replaces complex voltage-based sensing circuits with simple time-domain edge delay cells. The substitution of voltage measurement with time delay measurement fundamentally simplifies the circuit architecture, reducing transistor count and interconnect complexity while maintaining or improving sensing accuracy through the inherent noise immunity of time-domain signals.
Solution Approach 2:
By changing the output parameter from voltage to time delay, the patent eliminates the need for complex amplification, filtering, and analog-to-digital conversion circuits. The time-domain parameter naturally provides better signal-to-noise ratio, achieving higher sensing accuracy with simpler circuitry that requires fewer components and less chip area.
Data Source
AI summary
A memory unit with time domain edge delay accumulation for computing-in-memory applications is controlled by a first word line and a second word line. The memory unit includes at least one memory cell, at least one edge-delay cell multiplexor and at least one edge-delay cell. The at least one edge-delay cell includes a weight reader and a driver. The weight reader is configured to receive a weight and a multi-bit analog input voltage and generate a multi-bit voltage according to the weight and the multi-bit analog input voltage. The driver is connected to the weight reader and configured to receive an edge-input signal. The driver is configured to generate an edge-output signal having a delay time according to the edge-input signal and the multi-bit voltage. The delay time of the edge-output signal is positively correlated with the multi-bit analog input voltage multiplied by the weight.