3D Write Assist Scheme for SRAM Miswrite Reduction
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) become smaller and more complex, the decreasing operating voltages affect IC performance, leading to issues such as miswrites and misreads due to Static Noise Margin (SNM) effects in SRAM memory cells.
Innovation Solution
The implementation of a three-dimensional (3D) memory cell array with a separated write logic cell array, where each memory cell is electrically connected to a corresponding write logic cell. This configuration allows for the activation of only one memory cell during a write operation, rather than an entire row, thereby reducing SNM-related issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If operating voltage is decreased to enable smaller and more complex ICs, then device size and complexity are improved, but memory cell reliability deteriorates due to SNM effects causing miswrites and misreads
Solution Approach 1:
The memory system is segmented into selected memory cells and unselected memory cells through the use of word line control circuits. Only the selected memory cell receives the write voltage, while other cells in the same row are isolated. This segmentation allows the system to maintain small device size while improving reliability by preventing SNM-related miswrites in unselected cells.
Solution Approach 2:
The write voltage is applied locally only to the selected memory cell through controlled word line activation. Instead of applying voltage uniformly across the entire memory array, the system provides localized voltage enhancement precisely where needed (at the selected cell), thereby improving write reliability without affecting other cells and maintaining compact design.
2Speed
If write voltage is applied to entire row during write operation, then write speed is improved, but miswrites to unselected memory cells increase due to SNM effects
Solution Approach 1:
The word line control circuit segments the memory row into selected and unselected portions by activating only the specific word line corresponding to the target memory cell. This segmentation enables fast write operation to the selected cell while preventing voltage-induced miswrites in unselected cells, thus resolving the contradiction between write speed and write accuracy.
Solution Approach 2:
The word line control circuit acts as an intermediary between the write voltage source and the memory cells. It conditions and directs the write voltage exclusively to the selected memory cell through controlled word line activation, preventing the voltage from affecting unselected cells and thereby eliminating miswrites while maintaining fast write performance.
Data Source
AI summary
An integrated circuit includes a memory cell array, a row decoder configured to generate a first decoder signal, a column decoder configured to generate a second decoder signal and an array of write assist circuits electrically coupled to the row and column decoder and the memory cell array. Each write assist circuit is configured to set an operating voltage of a corresponding memory cell. The operating voltage corresponds to an output signal. Each write assist circuit includes a set of P-type transistors coupled together in parallel and further coupled to a supply voltage, and configured to set the output signal in response to an input control signal, and a first N-type transistor coupled to the set of P-type transistors. A first terminal of the first N-type transistor is configured to receive the input control signal. A second terminal of the first N-type transistor is coupled to the supply voltage.