Digital Storage TRIZ Cases
- Segmented Content-Addressable Memory Architecture for Low Power High Speed
A segmented content-addressable memory architecture uses independent sub-word circuits to minimize cycle time and reduce power consumption.
- Dual Dielectric Layer Strategy for MRAM Stack Metallization
Segmented dielectric deposition relaxes high aspect ratio memory stacks, preventing contact shorts and metal residues during metallization.
- System Bus Cycle Time Control via Signal Propagation Measurement
A time control unit measures signal propagation times on a system bus to define dynamic cycle times for connected modules.
- Semiconductor Memory Priority Control for Bus Sharing
Priority operation control portion selects data from semiconductor memory based on assigned levels, preventing exclusive bus usage by multiple masters.
- Ternary Memory Cell Arrangement Using Ferroelectric Transistors
A ternary memory cell arrangement uses two ferroelectric field-effect transistors to store data in three distinct logic states.
- Memory Decoding System Bit Line Coupling Compensation
A memory decoding system manages bit line voltages using specific PMOS and NMOS transistor control sequences during read operations.
- DRAM Refresh Rate Control via Temperature Change Rate Sensing
Memory controller adjusts DRAM refresh frequency based on measured temperature change rates to optimize power consumption.
- Double Row Buffer DRAM Access Latency Reduction
A double row buffer DRAM system decouples precharge and restore operations from data I/O lines to reduce critical path latency.
- Adjustable Write Pulse Generator for Chalcogenide Memory
Band-gap reference current circuits compensate temperature variations to maintain write current amplitude precision across varying cell technologies.
- Patterned Memory Page Activation for Power Reduction
Fractional row activation selectively energizes predicted storage cell patterns, reducing activation power consumption without increasing memory latency.
- Memory Mat Refresh Sequencing for Noise Reduction
A refresh control circuit generates non-adjacent wordline sequences to prevent noise interference between adjacent memory mats during refresh operations.
- D-MRAM Bit-Cell Data Replication via ME-MTJ
A D-MRAM bit-cell replicates volatile DRAM data into a magneto-electric magnetic tunnel junction using shared circuitry.