D-MRAM Bit-Cell Data Replication via ME-MTJ
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Solution Overview
Problem
Conventional non-volatile RAM technologies have slower read/write times compared to volatile RAM, and there is a need for data retention during power loss in portable computing devices, which is not adequately met by existing solutions.
Innovation Solution
The implementation of a dynamic-magneto random access memory (D-MRAM) bit-cell device with a magneto-electric magnetic tunnel junction (ME-MTJ) that replicates data from volatile DRAM to non-volatile MRAM, allowing for both independent operations while sharing electrical coupling and circuitry, enabling data backup and restoration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional non-volatile RAM is used to provide data retention during power loss, then data retention capability is improved, but read/write speed deteriorates
Solution Approach 1:
The memory system is segmented into two distinct memory types: volatile DRAM for fast read/write operations and non-volatile MRAM for data retention. Each memory type operates independently with its own optimized characteristics, allowing the system to achieve both high speed and data retention capability simultaneously.
Solution Approach 2:
The patent combines DRAM and MRAM technologies into a unified D-MRAM bit-cell structure that shares common circuitry including word lines, bit lines, access transistors, and sense amplifiers. This merging allows the system to leverage the speed advantages of DRAM while incorporating the non-volatile properties of MRAM, resolving the speed-retention contradiction.
2Speed
If volatile DRAM is used to achieve fast read/write operations, then read/write speed is improved, but data retention during power loss deteriorates
Solution Approach 1:
The system performs preliminary data replication by continuously copying data from the volatile DRAM portion to the non-volatile MRAM portion before power loss occurs. This preliminary action ensures that data is preserved in the MRAM portion even when power is removed, while the DRAM portion maintains fast read/write operations during powered operation.
Solution Approach 2:
The patent implements a copying mechanism where data stored in the DRAM portion of the bit-cell is replicated into the MRAM portion. This creates redundant copies of the same data in two different memory media with different characteristics, allowing the system to simultaneously achieve fast access speeds through DRAM and data retention through MRAM.
3Adaptability or versatility
If separate DRAM and MRAM devices are used to achieve both fast operations and data retention, then functional capability is improved, but device complexity increases
Solution Approach 1:
The patent merges DRAM and MRAM functionalities into a single integrated D-MRAM bit-cell device structure. The bit-cell shares common circuitry including word lines, bit lines, access transistors, and sense amplifiers between the DRAM and MRAM portions, reducing the need for separate dedicated circuitry and interconnections that would increase complexity.
Solution Approach 2:
The shared circuitry in the D-MRAM bit-cell serves multiple functions: the same word lines and bit lines access both DRAM and MRAM portions, the same access transistor controls data flow to both memory types, and the same sense amplifier reads data from both portions. This multi-functionality reduces overall device complexity while maintaining full functional capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides efficient data replication and retention by storing DRAM data in the MRAM portion of the D-MRAM bit-cell, ensuring data integrity during power loss and enabling fast read/write operations, thus addressing the limitations of conventional non-volatile RAM.
Implementation Method 1
a magneto-electric magnetic tunnel junction (ME-MTJ) configured to replicate data stored in the storage capacitor
Implementation Method 2
magneto-electric magnetic tunnel junction (ME-MTJ) configured to replicate data stored in the storage capacitor
Data Source
AI summary
In a particular implementation, a method of storing dynamic random-access memory (DRAM) data in respective magneto-electric magnetic tunnel junctions (ME-MTJ) of D-MRAM bit-cells of a D-MRAM bit-cell memory array, the method comprising: for each of the D-MRAM bit-cells: writing a first data value in a storage capacitor; and in a first cycle, providing a first voltage to a source line coupled to an ME-MTJ, wherein in response to the storage capacitor storing the first data value, the ME-MTJ is configured to store the first data value if the first voltage generates a voltage difference between first and second terminals of the ME-MTJ.


