Segmented Content-Addressable Memory Architecture for Low Power High Speed
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Solution Overview
Problem
Conventional content-addressable memory (CAM) devices face challenges in achieving high-speed operation while maintaining low power consumption, as segmentation methods increase delay time and pipeline approaches lead to significant power consumption and chip area expansion.
Innovation Solution
A semiconductor storage device with a segmented architecture, comprising a k-bit 1st-stage sub-word circuit and an (n-k)-bit 2nd-stage sub-word circuit connected via a segmentation circuit, allowing asynchronous or synchronous control and self-precharge capabilities to reduce power consumption and delay time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If segmentation method is used to divide word circuit, then power consumption is reduced, but delay time increases
Solution Approach 1:
The patent divides the word circuit into multiple independent sub-word circuits (first sub-word circuit and second sub-word circuit). Each sub-word circuit can operate independently and process search operations in parallel. This segmentation allows the system to reduce the delay time by processing parts of the search word simultaneously, while also reducing power consumption by activating only the necessary sub-word circuits based on the search pattern.
2Speed
If pipeline approach is used to improve throughput, then operation speed is improved, but power consumption and chip area increase significantly
Solution Approach 1:
The patent implements dynamic control of sub-word circuits through independent control signals. The control circuit can dynamically activate or deactivate specific sub-word circuits based on the search requirements. This dynamic operation allows the system to achieve high throughput by processing multiple search operations in parallel when needed, while consuming less power by activating only the minimum necessary circuits when the search space is smaller.
3Ease of operation
If conventional synchronous CAM is used with collective clock control, then control is simplified, but speed is determined by overall delay based on bit length
Solution Approach 1:
The patent segments the word circuit into multiple sub-word circuits that can be controlled independently. Each sub-word circuit has its own control signal, allowing them to operate at different speeds or be activated selectively. This segmentation enables the system to achieve higher throughput by processing different portions of the search word in parallel, rather than being constrained by the overall delay of a single synchronous operation.
Data Source
AI summary
A semiconductor storage device 1 includes: an input controller (3); and a content-addressable memory block (2) connected to the input controller (3). Each word circuit (4) of the content-addressable memory block (2) includes: a k-bit 1st-stage sub word (4a) connected to search line 1 (SL1) of the input controller (3); and an (n-k)-bit 2nd-stage sub word (4b) connected to search line 2 (SL2) of the input controller (3). The k-bit 1st-stage sub word (4a) and the (n-k)-bit 2nd-stage sub word (4b) are separated by a segmentation circuit (5). When the 1st-stage sub word outputs a match signal, the match result is stored in the segmentation circuit (5), and a plurality of local match circuits within the 2nd-stage sub word (4b) are operated.