Dual Dielectric Layer Strategy for MRAM Stack Metallization
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Solution Overview
Problem
Existing MRAM devices face challenges in efficiently forming high aspect ratio memory stacks with adequate dielectric coverage, leading to issues such as metal residues and contact shorts during metallization pattern formation.
Innovation Solution
A dielectric layer with poor coverage is initially formed to relax the high aspect ratio of memory stacks, followed by the deposition of an ILD layer, which helps in avoiding void exposure during planarization and reduces metal residues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a dielectric layer is formed with poor coverage to relax high aspect ratio memory stacks, then the aspect ratio is reduced and manufacturing becomes easier, but dielectric coverage becomes inadequate leading to metal residues and contact shorts
Solution Approach 1:
The dielectric layer formation is divided into two separate steps: first forming a dielectric layer with poor coverage to relax the high aspect ratio, then forming another dielectric layer to provide adequate coverage. This segmentation allows each layer to serve its specific function without compromising the other.
Solution Approach 2:
The first dielectric layer is formed preliminarily to relax the high aspect ratio of the memory stacks before the second dielectric layer is formed. This preliminary action prepares the structure for subsequent processing by reducing the aspect ratio, making the final dielectric coverage adequate and preventing metal residues and contact shorts.
2Productivity
If high aspect ratio memory stacks are formed, then device density is improved, but dielectric coverage becomes difficult to achieve leading to contact shorts
Solution Approach 1:
The dielectric layer formation is segmented into two steps: first forming a dielectric layer with poor coverage to relax the high aspect ratio, then forming another dielectric layer to provide adequate coverage. This segmentation allows the high aspect ratio structure to be maintained for device density while ensuring adequate dielectric coverage for reliability.
Solution Approach 2:
The first dielectric layer is formed preliminarily to relax the high aspect ratio before the second dielectric layer is formed. This preliminary action reduces the aspect ratio, enabling the second dielectric layer to achieve adequate coverage that prevents contact shorts while maintaining the high device density achieved through high aspect ratio stacking.
3Manufacturing precision
If adequate dielectric coverage is formed directly, then manufacturing precision is improved, but the process becomes more complex and costly
Solution Approach 1:
The dielectric layer formation is divided into two separate steps: first forming a dielectric layer with poor coverage to relax high aspect ratio memory stacks, then forming another dielectric layer to provide adequate coverage. While this increases the number of process steps, each step has a specific function and the overall process remains manageable compared to attempting to achieve adequate coverage in a single complex step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the formation of the ILD layer and metallization pattern, reducing metal residues and preventing contact shorts, while also being cost-effective and suitable for high throughput.
Implementation Method 1
depositing a first dielectric layer over the first and second memory cells, such that the first dielectric layer has a void between the first and second memory cells
Implementation Method 2
depositing a second dielectric layer over the first dielectric layer
Data Source
AI summary
A method for fabricating a semiconductor device is provided. The method includes forming a first memory cell and a second memory cell over a substrate, wherein each of the first and second memory cells comprises a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element; depositing a first dielectric layer over the first and second memory cells, such that the first dielectric layer has a void between the first and second memory cells; depositing a second dielectric layer over the first dielectric layer; and forming a first conductive feature and a second conductive feature in the first and second dielectric layers and respectively connected with the top electrode of the first memory cell and the top electrode of the second memory cell.