Double Row Buffer DRAM Access Latency Reduction
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Solution Overview
Problem
Conventional DRAM architectures face increased access latency and write recovery latency due to the serialization of commands, particularly in the precharging of bit lines, which creates a bottleneck in the pipeline and limits the efficiency of memory operations.
Innovation Solution
The implementation of a Double Row Buffer DRAM (DRB-DRAM) system, where two row buffers are used instead of a single row buffer, allowing for mutual exclusive connection to bit lines and data I/O lines, enabling overlapping of precharge and restore operations with data I/O, thereby reducing critical path latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single row buffer is used in conventional DRAM architecture, then the device complexity is reduced, but the access latency and write recovery latency increase due to command serialization
Solution Approach 1:
The single row buffer is segmented into multiple independent row buffers (first row buffer, second row buffer, third row buffer, etc.), each capable of independently storing row data and being accessed simultaneously. This segmentation eliminates the command serialization bottleneck by allowing parallel operations on different buffers, thereby reducing access latency while maintaining manageable device complexity through modular architecture.
Solution Approach 2:
The patent introduces a new dimension of parallelism by organizing multiple row buffers in a way that allows simultaneous access through different buffer indices. Instead of sequential access through a single buffer, the system can now access multiple buffers concurrently, effectively adding a temporal parallelism dimension that reduces latency without proportionally increasing complexity.
2Loss of time
If multiple row buffers are implemented to reduce access latency, then the access latency decreases, but the device complexity increases
Solution Approach 1:
Each row buffer is designed with universal functionality to handle multiple operations (reading, writing, precharging) independently. The buffers can be selectively activated based on access patterns, allowing the system to achieve parallelism without requiring complex specialized circuitry for each buffer. This multi-functionality approach reduces the overall complexity increase by reusing the same buffer structure across multiple instances.
Solution Approach 2:
The system performs preliminary actions by precharging multiple bit line sets in advance and maintaining multiple row buffers ready for simultaneous access. This preliminary preparation eliminates the need for sequential command execution, as the infrastructure is already in place to handle parallel operations, thereby reducing access latency without requiring complex real-time decision-making logic.
3Device complexity
If command serialization is maintained in conventional DRAM, then the device complexity is reduced, but the productivity decreases due to pipeline bottlenecks
Solution Approach 1:
The command processing pipeline is segmented into multiple parallel paths, each handling different row buffer operations simultaneously. Instead of a single sequential command stream, the system can issue multiple commands to different row buffers in parallel, eliminating the pipeline bottleneck and significantly improving memory operation efficiency while keeping the command scheduling logic relatively simple through independent buffer management.
Solution Approach 2:
The patent enables continuous useful action by allowing overlapping of memory operations across multiple row buffers. While one buffer is being accessed, another can be precharged or written to, ensuring that the memory subsystem is continuously productive without idle pipeline stages. This continuous operation dramatically improves productivity without requiring complex inter-buffer coordination.
Data Source
AI summary
The present disclosure relates to a dynamic random access memory (DRAM) array, which comprises a plurality of bit lines connectable, respectively, to at least two row buffers of the DRAM array. The two row buffers are respectively connectable to data input/output (I/O) lines and are configured to electrically connect the two row buffers to the bit lines and data I/O lines in a mutually exclusive manner.