Patterned Memory Page Activation for Power Reduction
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Solution Overview
Problem
Row activation in integrated-circuit memory devices is time-consuming due to high power consumption, as most data transferred during row activation remains untouched in subsequent column operations, leading to inefficiencies in memory access operations.
Innovation Solution
Implementing patterned, fractional row activation by selectively activating only predicted or predetermined patterns of storage cells within a row, using activation mode logic and registers to optimize energy usage without increasing memory latency, by dynamically or statically predicting which combinations of cells will yield the highest number of page hits per quantum of activation energy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If traditional row activation is used to transfer data from storage cells to sense amplifiers, then memory access can be performed, but power consumption increases significantly because most activated data remains untouched
Solution Approach 1:
The patent extracts only the necessary portion of data from the storage row by activating specific column groups based on predicted access patterns. Instead of transferring the entire row to sense amplifiers, only the relevant segments are activated and transferred, eliminating waste of energy on untouched data while maintaining full memory access capability through predictive column group activation.
Solution Approach 2:
The patent applies partial action by activating only a fraction of the row (specific column groups) rather than the entire row. The activation is partially excessive in that it activates more columns than immediately needed based on current access, but less than the full row, with the expectation that subsequent accesses will hit the pre-activated columns, thus reducing overall power consumption while maintaining access efficiency.
2Productivity
If the number of columns per row is increased to improve page hit likelihood, then spatial/temporal locality is exploited better, but power consumption during row activation increases due to activating more storage cells
Solution Approach 1:
The patent segments the row into multiple column groups and activates only specific segments based on predicted access patterns. This segmentation allows the system to maintain high page hit rates by pre-activating relevant segments while avoiding energy waste on segments that won't be accessed, effectively decoupling the number of activated columns from the total columns per row.
Solution Approach 2:
The patent applies local quality by making different column groups have different activation states based on their predicted utility. Instead of uniform activation across the entire row, specific local regions (column groups) are activated with higher probability based on access pattern predictions, optimizing the balance between page hit rate and power consumption locally rather than globally.
3Loss of energy
If patterned fractional row activation is implemented to reduce power consumption, then activation energy is optimized, but device complexity increases due to prediction logic and activation mode registers
Solution Approach 1:
The patent uses preliminary action by pre-calculating and storing activation patterns in prediction logic and activation mode registers before actual memory access operations. The complex prediction and pattern generation is performed in advance, allowing the actual row activation to follow pre-determined patterns, thus reducing runtime complexity while maintaining energy efficiency benefits.
Data Source
AI summary
Row activation operations within a memory component are carried out with respect to patterns of storage cells that constitute a fraction of a row and that have been predicted or predetermined to yield a succession of page hits, thus reducing activation power consumption without significantly increasing memory latency. The patterns of activated storage cells may be predicted or predetermined statically, for example, in response to user input or configuration settings that specify activation patterns to be applied in response to memory request traffic meeting various criteria, or dynamically through run-time evaluation of sequences of memory access requests.