Memory Mat Refresh Sequencing for Noise Reduction
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Solution Overview
Problem
In memory systems, the refresh operation of memory cells can lead to noise interference between adjacent memory mats sharing components, causing data corruption during the refresh process, necessitating a non-adjacent sequence of refreshes to prevent such issues.
Innovation Solution
A refresh control circuit generates a sequence of refresh addresses that ensures each memory mat is refreshed with at least one other mat between sequentially refreshed mats, both within and between sets of memory mats, using a logic-based approach to update mat addresses and control the refresh sequence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory mats are refreshed in sequential order, then refresh operation is simple and fast, but noise interference occurs between adjacent memory mats causing data corruption
Solution Approach 1:
The refresh operation is segmented into multiple independent refresh sequences, each handling non-adjacent memory mats. The refresh control circuit divides the memory mat array into separate refresh groups, allowing parallel execution of refresh operations without adjacent mat interference, thus maintaining both speed and data integrity.
Solution Approach 2:
The refresh control circuit dynamically generates refresh addresses using a non-sequential addressing scheme. Instead of fixed sequential ordering, the circuit dynamically calculates refresh addresses to skip adjacent mats, adapting the refresh sequence in real-time to prevent noise interference while maintaining efficient refresh coverage.
2Reliability
If non-adjacent memory mats are refreshed in sequence, then noise interference is reduced, but refresh operation complexity increases
Solution Approach 1:
The refresh control circuit employs self-service mechanisms by automatically generating non-sequential refresh addresses through internal logic circuits. The circuit autonomously determines the refresh sequence without external intervention, using built-in address generation logic that inherently produces non-adjacent mat patterns, thereby reducing overall system complexity while maintaining data integrity.
3Device complexity
If refresh addresses are generated sequentially, then address generation is simple, but adjacent memory mats are refreshed causing noise interference
Solution Approach 1:
Instead of generating sequential addresses and then skipping, the invention inverts the approach by directly generating non-sequential addresses that inherently skip adjacent mats. The address generation logic is designed to produce patterns like 0, 2, 4, 6 or 0, 3, 6, 9, eliminating the need for sequential generation followed by interference mitigation, thus reducing noise while keeping complexity manageable.
Data Source
AI summary
Embodiments of the disclosure are drawn to apparatuses and methods for a sequence of refreshing memory mats. During a refresh operation, wordlines of the memory may be refreshed in a sequence. Groups of wordlines may be organized into memory mats. In order to prevent noise, each time a wordline in a memory mat is refreshed, the next wordline to be refreshed may be in a mat which is not physically adjacent to the mat containing the previously refreshed wordline.