Ternary Memory Cell Arrangement Using Ferroelectric Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional content-addressable memory (CAM) cells, particularly binary CAM cells, lack flexibility in data matching due to limited logic states, whereas ternary CAM cells introduce a 'do not care' state, but existing ternary CAM cell designs often require a large number of transistors and are not efficiently integrated with logic circuits, especially at advanced feature sizes.
Innovation Solution
A ternary memory cell arrangement utilizing two ferroelectric field-effect transistors (FeFETs) with a remanent-polarizable layer, allowing for non-volatile data storage and efficient integration with logic circuits, even at feature sizes less than 45 nm, by employing a NOR or NAND configuration to achieve three distinct matching states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional binary CAM cells are used, then the memory cell structure is simple, but the data matching flexibility is limited
Solution Approach 1:
The patent introduces a third logic state (X state or do-not-care state) in addition to the conventional binary 0 and 1 states. This parameter change in the logic state system enables the memory cell to provide flexible data matching capabilities, where the X state can match both 0 and 1, thus resolving the contradiction between matching flexibility and structural complexity.
2Adaptability or versatility
If existing ternary CAM cell designs are used, then data matching flexibility is improved, but the number of transistors increases and integration efficiency decreases
Solution Approach 1:
The patent merges the storage function and the matching function into a single integrated memory cell structure. By combining these functions that were previously separated in conventional designs, the patent achieves ternary logic functionality with reduced transistor count and improved integration efficiency, directly addressing the contradiction between data matching flexibility and device complexity.
Solution Approach 2:
The memory cell is designed with multi-functionality, serving as both a storage element and a matching element simultaneously. This universal design allows the same structure to perform multiple functions (storage and comparison), reducing the overall complexity and transistor count while maintaining ternary data matching flexibility.
3Adaptability or versatility
If existing ternary CAM cell designs are used, then three logic states are achieved, but integration with logic circuits at advanced feature sizes is inefficient
Solution Approach 1:
The patent employs parameter changes in the transistor design and configuration to enable efficient integration at advanced feature sizes. By optimizing the physical and electrical parameters of the memory cell components, the design achieves both ternary logic state capability and improved manufacturability/integration efficiency at smaller feature sizes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces chip area and costs while providing flexible data matching capabilities and efficient integration with logic circuits, enhancing the performance and scalability of memory technologies.
Implementation Method 1
two ferroelectric field-effect transistors (FeFETs) with a remanent-polarizable layer, allowing for non-volatile data storage
Data Source
AI summary
In various embodiments, a ternary memory cell is provided, the ternary memory cell including: a first ferroelectric memory cell and a second ferroelectric memory cell in a parallel or serial arrangement, wherein each of the first ferroelectric memory cell and the second ferroelectric memory cell is switchable into a first ferroelectric memory cell state and a second ferroelectric memory cell state; and wherein a first matching state is defined by the first ferroelectric memory cell in the first ferroelectric memory cell state and the second ferroelectric memory cell in the second ferroelectric memory cell state, wherein a second matching state is defined by the first ferroelectric memory cell in the second ferroelectric memory cell state and the second ferroelectric memory cell in the first ferroelectric memory cell state, and wherein a third matching state is defined by the first ferroelectric memory cell and the second ferroelectric memory cell being in the same ferroelectric memory cell state.