Semiconductor Memory Priority Control for Bus Sharing
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Solution Overview
Problem
Existing memory access control systems for semiconductor memory apparatuses with multiple bus masters struggle to dynamically change priorities of reading requests and prevent exclusive use of the memory bus, leading to inefficiencies in data transfer and potential bottlenecks.
Innovation Solution
A semiconductor memory apparatus with a main memory that stores data along with priority information, a read request input portion, a data reading portion, and a priority operation control portion that dynamically selects and outputs data based on changing priorities, ensuring flexible priority management and non-exclusive memory bus usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory access control systems use fixed priority methods for multiple bus masters, then the control circuit constitution remains simple, but the system cannot dynamically adjust priorities leading to memory bus inefficiency and exclusive usage
Solution Approach 1:
The patent implements dynamic priority assignment where the priority of each bus master is not fixed but can be changed based on the type of data being transferred. The control circuit dynamically selects priorities from multiple levels (first, second, third priorities) depending on whether the data is instruction data, constant data, or variable data, allowing the system to adapt to different operational requirements without requiring a completely complex control structure
Solution Approach 2:
The system changes the priority parameter of bus masters based on the data type being accessed. By associating different priority levels with different data types (instructions, constants, variables), the system can adjust priorities flexibly without fundamentally changing the control circuit architecture, thus resolving the contradiction between adaptability and complexity
2Productivity
If the system exclusively uses the memory bus for data transfer, then data transfer efficiency is maximized, but other bus masters cannot access the memory bus causing system bottlenecks
Solution Approach 1:
The control circuit periodically evaluates and switches between different priority assignments based on the current data transfer requirements. By implementing periodic priority reassignment rather than exclusive or fixed priority, the system can maximize data transfer efficiency during critical periods while still allowing other bus masters to access the memory bus during less critical periods, thus balancing efficiency with shared access capability
Solution Approach 2:
The system allows different data types to self-determine their priority level through predefined associations. Instruction data automatically receives first priority, constant data receives second priority, and variable data receives third priority, eliminating the need for complex centralized arbitration and enabling efficient self-service data transfer while maintaining bus sharing capability
3Use of energy by stationary object
If multiple processor cores share the same memory bus, then power consumption is reduced, but contention for bus access increases requiring complex priority control
Solution Approach 1:
The patent implements a parameter-based priority control system where the priority parameter changes based on data type rather than requiring complex dynamic arbitration. By pre-defining priority associations with data types (instructions=first priority, constants=second priority, variables=third priority), the system manages multiple processor cores sharing the memory bus with relatively simple control logic, balancing power efficiency with control complexity
Data Source
AI summary
In order to provide a semiconductor memory apparatus which can flexibly change the priority of reading requests when the reading request is issued and which do not exclusively use the memory bus, a semiconductor memory apparatus includes: a main memory which stores data at an address while maintaining a corresponding relationship between the data and the address; a read request input portion receiving a read request which maintains a corresponding relationship between address information that is referred to when reading the data and priority information that indicates priority for reading the data; a read data storing portion which stores the data and priority while maintaining a corresponding relationship thereof; a data reading portion reads the data corresponding to address information which is input by the read request input portion from the main memory; a read data registration portion storing both the priority information input by the read request input and the data read by the data reading portion to the read data storing portion while maintaining a corresponding relationship between the priority information and the data read; and a priority operation control portion which chooses and outputs the data with a highest priority among the priority information and the data that are stored in the read data storing portion while maintaining a corresponding relationship between the priority information and the data.