3DIC Die-to-Die ESD Layout Using a Combo SCR Structure
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Solution Overview
Problem
The challenge in 3D integrated circuits (3D ICs) is the generation and accumulation of electrostatic charges during processes like plasma etching, which can cause damage to components and interconnects when released suddenly, necessitating an efficient and space-friendly electrostatic discharge (ESD) solution.
Innovation Solution
A semiconductor package design incorporating a first die with an internal circuit, an ESD protection circuit, and a Silicon Controlled Rectifier (SCR) component, laterally spaced from the internal circuit, to efficiently discharge accumulated electrostatic charges, using a combo SCR structure that includes charge dissipation elements and SCR components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ESD protection circuits are used in 3D ICs, then electrostatic discharge protection is provided, but significant penalty areas are consumed and power buses are tapped
Solution Approach 1:
The patent combines the ESD protection circuit with the SCR component into a single integrated structure. The ESD protection circuit shares common elements with the SCR, such as the anode, cathode, and substrate connections, eliminating the need for separate power bus taps and reducing the total area required. This merging approach allows the ESD protection function to be achieved without consuming additional penalty areas or requiring separate power bus connections.
2Productivity
If plasma etching processes are used for TSV formation, then high integration density is achieved, but electrostatic charges accumulate causing potential damage
Solution Approach 1:
The patent implements ESD protection circuits and SCR components during the die fabrication process, before the dies are stacked and before plasma etching processes are performed. This preliminary placement of protection structures ensures that when plasma etching is subsequently used to form TSVs through the stacked dies, any accumulated electrostatic charges will have a predetermined safe discharge path, preventing damage to the high-density interconnects and components that were already formed.
3Reliability
If lateral spacing is provided between ESD circuit and internal circuit, then discharge paths are covered without power bus tapping, but device complexity increases
Solution Approach 1:
The SCR component serves multiple functions simultaneously: it acts as the ESD protection element, provides the discharge path for electrostatic charges, and eliminates the need for separate power bus connections. By making the SCR multi-functional, the patent achieves comprehensive discharge path coverage through lateral spacing while avoiding the complexity of additional separate protection circuits and their associated power bus requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The combo SCR structure effectively discharges electrostatic charges, improving integration and reducing the size of the package by saving penalty areas, enhancing ESD/PID discharge performance, and ensuring all discharge paths are covered without tapping into power buses.
Implementation Method 1
the generation and accumulation of electrostatic charges during processes like plasma etching, which can cause damage to components and interconnects when released suddenly, necessitating an efficient and space-friendly electrostatic discharge (ESD) solution
Implementation Method 2
A semiconductor package design incorporating a first die with an internal circuit, an ESD protection circuit, and a Silicon Controlled Rectifier (SCR) component, laterally spaced from the internal circuit, to efficiently discharge accumulated electrostatic charges
Data Source
AI summary
A semiconductor package includes at least a first die. The first die includes an internal circuit disposed on a substrate, an electrostatic discharge (ESD) protection circuit disposed on the substrate but laterally spaced from the internal circuit and including a first charge dissipation element, and a first Silicon Controlled Rectifier (SCR) laterally adjacent to and spaced from the first charge dissipation element.