3DIC Scan Architecture for Hybrid-Bond Interconnect Defect Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing 3D integrated circuit (3DIC) testing methods face challenges in efficiently detecting defects and ensuring high-density, low-leakage interconnects, particularly in hybrid bonded structures, which are cost-effective and compatible with die-to-die and wafer-on-wafer bonding.
Innovation Solution
Implementing a serial cross-bar scan architecture with hybrid bonding and a scan chain mechanism that includes wrapper cells, flip-flops, and multiplexers to create a shift register across stacked dies, allowing for inter-die and intra-die testing, and using clock frequency sweeping to detect defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If hybrid bonding is used for die-to-die and wafer-on-wafer integration, then cost-effectiveness and high-density interconnects are achieved, but defect detection becomes more difficult
Solution Approach 1:
The patent segments the interconnect structure into multiple accessible layers and regions, allowing test signals to reach different portions of the hybrid bonded interconnects through multiple pathways. This segmentation enables defect detection in previously inaccessible high-density interconnect regions without compromising the cost-effective hybrid bonding approach.
2Quantity of substance
If high-density interconnects are implemented in hybrid bonded structures, then integration density is improved, but leakage increases
Solution Approach 1:
The patent introduces intermediary test structures and isolation mechanisms that mediate between the high-density interconnects and the test signal pathways. These intermediaries allow leakage current to be isolated and measured separately from functional operations, enabling high-density interconnect implementation without excessive leakage affecting overall device performance.
3Measurement precision
If scan chain mechanism with wrapper cells is implemented across stacked dies, then defect detection capability is enhanced, but device complexity increases
Solution Approach 1:
The patent implements universal wrapper cell designs that serve multiple functions: they act as scan chain elements for defect detection, as signal routing elements for normal operation, and as isolation elements for leakage control. This multi-functionality enhances defect detection capability while minimizing the increase in device complexity by reusing the same structural elements across different operational modes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances defect detection in 3DICs by identifying both hard and resistive defects through comprehensive testing, reducing leakage and power consumption, and optimizing die size, while maintaining high-density interconnects.
Implementation Method 1
direct Cu—Cu thermo-compression bonding
Data Source
AI summary
A method of using a semiconductor device includes receiving a signal at a first latch of a first plurality of latches on a first die. The method further includes relaying the signal from the first latch to a second latch of a second plurality of latches on a second die electrically connected to the first die. The method further includes relaying the signal from the second latch to a third latch of the second plurality of latches. The method further includes relaying the signal from the third latch to a fourth latch of the first plurality of latches.