Digital Circuit Testing TRIZ Cases
- Selectable Lockup Latches for Multi-Die Scan Chain Clock Skew
Selectable lockup latches compensate clock skew between multi-die scan chains, preventing timing violations and improving test coverage.
- AI Embedding Vector Calibration for DUT Tuning Without Retraining
Pretrained embeddings and a vector database retrieve optimal DUT tuning parameters from waveform tensors, avoiding neural network retraining.
- CAN Bus In-System Configuration for Dynamic Node ID Assignment
A leader device programs CAN nodes over the bus to assign IDs by location, cutting assembly logistics and preserving accurate node mapping.
- On-Chip Test Data Distribution for Parallel Multi-Die Testing
An on-chip test distribution module shares few pins across multiple dies, enabling parallel test application and shorter test time.
- FPGA Signal Capture Reconfiguration for Error Waveform Analysis
When FPGA errors occur, partial reconfiguration shifts signal capture points and reruns processing to collect broader waveform data without restart.
- Executable Noise Injection for Side-Channel Attack Resistance
Triggered noise injection obscures timing and electromagnetic signatures, protecting executables from side-channel attacks with limited overhead.
- Fuse IP BIST Check Bits for Parallel Blown Error Detection
Check bits and parallel logic let fuse IP self-test detect blown errors across multiple fuse bits without reading a fuse file.
- On-Die Noise Measurement Circuit for Shift-Phase Scan Testing
Partitioned on-die noise sensing with a free-running clock captures local voltage hotspots during shift and capture phases in ATE and IST.
- Signal Chain Auto-Configuration Using Figures of Merit
Automatic signal-chain tuning uses stored figures of merit and signal moments to cut setup time while reducing noise and distortion.
- Clock Duty-Cycle Analysis Circuit for High-Speed Serial I/O
Tap-line voltage sensing identifies and corrects duty-cycle errors in high-speed serial I/O clocks without laser probe tools.
- 3DIC Scan Architecture for Hybrid-Bond Interconnect Defect Testing
A cross-die scan chain with wrapper cells and clock sweeping improves defect detection in hybrid-bonded 3DIC interconnects.
- Pipeline Sequential Circuit Testing With Adjustable Clock Pulses
Multiple clock paths with phase and pulse-width adjustment verify pipeline sequential circuits against real timing variation and improve yield.
- SSD PCB Sideband Pin Remapping for Boundary Scan Access
Remapped SSD PCB sideband pins let ATE enter boundary scan mode and detect poor connections and manufacturing defects without extra test pins.
- Clock-Gated Test-Point Flop Sharing to Reduce Wiring Congestion
Grouping test-point nodes by common clock-gates lets EDA tools share flops and place them nearer logic, reducing interconnect congestion.
- Probe Tip Characterization Data for Precise Measurement Correction
Reduced probe-tip characterization data combines with instrument defaults to correct tip-to-tip transmission variation without large memory.
- Circuit Pin Name Verification Using EDA Report Comparison
Automated comparison of EDA-generated pin reports with stored component data catches pin naming errors faster and more accurately in circuit design.
- Embedded-Command Scan Frames for Low-Contact IC Testing
Serial scan frames embed test commands and data to cut tester contacts while preserving high-rate, parallel IC testing.
- Single-Wire Bus Scan Testing Without Extra External Pins
Internal driver circuitry reuses bus-connected pins for scan inputs and outputs, enabling full scan testing without extra external pins.
- Protocol-Aware Trigger Generation for Low-Latency Test Equipment
Local protocol-aware trigger generation cuts transmission delay and improves timing accuracy in multi-site automated test equipment.