Embedded-Command Scan Frames for Low-Contact IC Testing
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Solution Overview
Problem
Existing integrated circuit testing methods require a large number of contacts between testers and integrated circuits, limiting parallel testing capabilities and efficiency, especially when using low-cost testers.
Innovation Solution
A test interface and architecture that reduces the number of contacts required by utilizing a serial-to-parallel conversion of scan frames, incorporating control information within the scan patterns, and employing differential and bidirectional signaling to facilitate efficient scan testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional parallel scan testing is used, then testing efficiency can be improved, but the number of contacts required between tester and integrated circuit increases
Solution Approach 1:
The patent segments the test data into serial scan frames that are multiplexed over a single contact. Each scan frame contains control information and test data that are sequentially transmitted, allowing parallel testing functionality to be achieved through time-division multiplexing rather than requiring multiple simultaneous contacts
Solution Approach 2:
The single scan input contact serves multiple functions: it carries both test data and control information, supports both serial and parallel operation modes, and enables multiple integrated circuits to be tested through time-multiplexed access. This multi-functional approach eliminates the need for separate dedicated contacts for each function
2Device complexity
If the number of contacts is reduced, then device complexity is decreased, but data rate may be compromised
Solution Approach 1:
The patent employs periodic transmission of scan frames at high speed over the single contact. By organizing data into periodic frames with control information and test data, the system achieves high effective data rates through rapid sequential transmission, compensating for the reduced parallelism of having fewer contacts
Solution Approach 2:
The system dynamically changes operational parameters including frame size, transmission rate, and multiplexing patterns to optimize data rate. By adjusting these parameters based on testing requirements, the system maintains high data rates while using a reduced number of contacts
Data Source
AI summary
Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.