On-Die Noise Measurement Circuit for Shift-Phase Scan Testing
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Solution Overview
Problem
Current methods for on-die noise measurement during ATE and IST are inadequate, leading to false compliance due to sensor monitor measurements that do not account for local noise hotspots and cannot determine the net effect on on-die logic, resulting in inefficient low-power solution optimization and increased test costs.
Innovation Solution
A technique that measures on-die noise granularly by placing a noise measurement system in partitions expected to cause the most noise, using a free-running clock, enable generation logic, and a counter to characterize voltage noise during both shift and capture phases, allowing precise optimization of low-power settings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If sensor monitor measurements are used for on-die noise measurement, then measurement coverage is provided, but measurement precision is insufficient due to inability to detect local noise hotspots and determine net effect on on-die logic
Solution Approach 1:
The chip is divided into multiple partitions, with each partition containing its own noise measurement circuit. This segmentation allows localized noise measurement in each partition, enabling detection of local noise hotspots while maintaining overall coverage. The measurement system is distributed across partitions rather than using a single centralized sensor, thereby improving measurement precision without requiring a single complex centralized system.
Solution Approach 2:
A delay element is introduced as an intermediary between the noise measurement circuit and the logic circuit. The delay element allows the noise measurement circuit to measure the noise effect on the logic circuit by comparing signals at different time points. This intermediary enables precise measurement of the net effect of noise on logic operation without directly interfering with the logic circuit itself.
2Measurement precision
If comprehensive noise measurement during both shift and capture phases is implemented, then measurement completeness is improved, but test time increases
Solution Approach 1:
The noise measurement function is merged with the existing scan test backbone infrastructure. The noise measurement circuits are integrated into the scan test flow, sharing the same test access mechanisms and control structures. This merging allows comprehensive noise measurement during both shift and capture phases without requiring separate dedicated measurement time, thereby maintaining measurement completeness while minimizing additional test time.
3Measurement precision
If noise measurement system is placed in all partitions, then measurement coverage is maximized, but device complexity and area increase
Solution Approach 1:
Noise measurement circuits are selectively placed only in partitions that are expected to cause or experience significant noise, rather than uniformly in all partitions. This local quality approach concentrates measurement resources in critical areas (noise hotspots) while reducing overall system area. The measurement coverage is optimized to match the actual noise distribution pattern on the chip.
Data Source
AI summary
Introduced herein is a technique that reliably measures on-die noise of logic in a chip. The introduced technique places a noise measurement system in partitions of the chip that are expected to cause the most noise. The introduced technique utilizes a continuous free-running clock that feeds functional frequency to the noise measurement circuit throughout the noise measurement scan test. This allows the noise measurement circuit to measure the voltage noise of the logic during a shift phase, which was not possible in the conventional noise measurement method. Also, by being able to measure the voltage noise during a shift phase and hence in both phases of the scan test, the introduced technique can perform a more comprehensive noise measurement not only during ATE testing but as part of IST in the field.