Clock-Gated Test-Point Flop Sharing to Reduce Wiring Congestion
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Solution Overview
Problem
Modern circuit designs face inefficiencies due to extensive interconnect wiring between numerous test-point flops and nodes, which are distributed across the physical layout, leading to wiring congestion.
Innovation Solution
A system that allocates test-point flops to sharing groups based on common clock-gates, associating each test-point node with a clock-gate in the circuit netlist, and generates a circuit layout that physically proximally locates test-point flops with their respective nodes, using an EDA application.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple test-point nodes are coupled to a single test-point flop via scan-chains, then the number of test-point flops is reduced, but extensive interconnect wiring is required between the test-point flops and the distributed test-point nodes
Solution Approach 1:
The patent merges multiple test-point nodes that share a common clock-gate into a single test-point sharing group, which is then coupled to one test-point flop. This consolidation reduces the total number of test-point flops required while the clock-based grouping strategy minimizes interconnect wiring by organizing nodes according to their clock-domain relationships.
Solution Approach 2:
The patent applies local quality by creating distinct test-point sharing groups based on clock-gate associations, where each group has specific characteristics (common clock-gate) that differentiate it from other groups. This localized organization allows for optimized wiring within each group while maintaining the overall reduction in flop quantity.
2Adaptability or versatility
If test-point nodes are distributed across the physical layout of the circuit, then coverage of functional logic is improved, but extensive interconnect wiring is required to connect all nodes to test-point flops
Solution Approach 1:
The patent segments the distributed test-point nodes into multiple test-point sharing groups based on their clock-gate associations. Each segment (sharing group) is then connected to a dedicated test-point flop, which reduces the overall interconnect wiring complexity while preserving the distributed coverage benefit across the physical layout.
3Ease of manufacture
If test-point flops are physically located away from their associated test-point nodes, then circuit layout flexibility is improved, but wiring congestion increases
Solution Approach 1:
The patent performs preliminary action by allocating test-point flops to specific test-point sharing groups during the design phase based on clock-gate relationships. This pre-allocation strategy enables the circuit layout tool to place test-point flops in optimal locations that balance layout flexibility with minimized wiring congestion to their associated nodes.
Data Source
AI summary
A system includes a memory that stores instructions and receives a circuit netlist, and includes a processing unit that accesses the memory and executes the instructions. The instructions include an EDA application that includes a test-point flop allocation module that divide the test-point nodes into a plurality of test-point sharing groups in which each of the test-point nodes is associated with one of the clock-gates that is common to each of at least one flip-flop of the portion of the functional logic coupled to each of the respective test-point nodes in the test-point sharing group. The test-point flop allocation module can further allocate one of the test-point flops to each of the test-point sharing groups. The EDA application also includes a circuit layout module configured to generate a circuit layout associated with the circuit design based on the circuit netlist. The circuit layout is employable to fabricate an IC chip.