Pipeline Sequential Circuit Testing With Adjustable Clock Pulses
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Solution Overview
Problem
The complexity and dispersion of advanced manufacturing processes in mining machine processors lead to deviations between simulated and actual working conditions, causing pipeline clocks to fail design requirements, which limits yield and performance.
Innovation Solution
A test circuit with a clock driving module providing adjustable clock signals through multiple paths with varying phases and a verification module comparing outputs to a reference device, allowing for precise timing adjustments to meet design requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conservative clock tree structure is selected based on SPICE simulation and static timing analysis, then design reliability is improved, but actual processor performance deteriorates due to deviation between simulation and manufacturing reality
Solution Approach 1:
The patent applies preliminary action by incorporating a test circuit into the processor design that proactively identifies and characterizes clock signal issues before they affect actual processing performance. The test circuit pre-tests clock paths and generates calibration data that can be used to adjust clock tree parameters, thereby preventing performance degradation while maintaining design reliability.
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting clock tree parameters (such as clock gate enable/disable states, buffer insertion, or timing delays) based on test results from the integrated test circuit. This allows the system to optimize clock distribution parameters to match actual manufacturing variations, improving processor performance while maintaining the conservative design approach.
2Productivity
If advanced manufacturing processes are used to improve processor performance, then production capability is improved, but process complexity and dispersion increase causing deviation from simulation conditions
Solution Approach 1:
The patent applies feedback by using the test circuit to continuously monitor and measure actual clock signal characteristics in the manufactured processor. This feedback information about timing deviations, signal integrity, and path delays is then used to calibrate and adjust clock tree parameters, compensating for manufacturing process variations and aligning actual performance with simulation predictions.
Solution Approach 2:
The patent applies self-service by enabling the processor to self-test and self-calibrate its clock distribution system through the integrated test circuit. The system automatically identifies timing issues and adjusts its own clock parameters without requiring external intervention, thereby managing process complexity internally while maintaining high production capability.
3Measurement precision
If multiple clock paths with different phases are provided to test sequential devices, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing a test circuit that can perform multiple testing functions using the same hardware resources. The clock distribution network with multiple phases serves dual purposes: it provides clock signals for normal processor operation and simultaneously enables precise timing measurements for testing sequential devices. This multi-functionality reduces test circuit complexity while maintaining high measurement precision.
Data Source
AI summary
A test circuit (300, 300′, 400, 500, 600, 700, 800), including: a test sequence providing module (301), configured to provide a test sequence (PRBS) to a to-be-tested sequential device (303); a clock driving module (307, 407, 507, 607, 707, 807), configured to provide a clock signal (759) to the to-be-tested sequential device (303), which includes a first clock driving circuit (610, 710), wherein the first clock driving circuit (610, 710) includes: a plurality of first clock paths (421, 423) which respectively provide corresponding clock signals (759); and a logic unit (427, 715) which generates, based on at least part of the clock signals (759) provided by the plurality of first clock paths (421, 423), a first clock signal with an adjusted pulse width, for the to-be-tested sequential device (303); and a verification module (305, 405, 805), configured to verify an output of the to-be-tested sequential device (303).