Circuit Pin Name Verification Using EDA Report Comparison
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Solution Overview
Problem
In circuit design, manual verification of chip pin names is inefficient and prone to errors, leading to potential misnaming and circuit rearrangement, which can be costly and time-consuming.
Innovation Solution
A method and system utilizing a components pin report generated by running a circuit with tools like Allegro PCB Designer and OrCAD, comparing it against stored component specifications to verify pin names, ensuring correct naming through logical output analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If manual verification of chip pin names is performed, then verification can be done with simple tools, but verification efficiency is low and error rate is high
Solution Approach 1:
The patent replaces manual mechanical verification processes with automated electronic verification systems. The EDA tool automatically extracts pin information from circuit diagrams, compares it with component databases, and verifies naming conventions without human intervention, thereby improving both efficiency and accuracy simultaneously
Solution Approach 2:
The patent introduces an intermediary verification system that acts as a bridge between the circuit design and final implementation. This intermediary automated verification process uses EDA tools to mediate the checking of pin names against component specifications, preventing errors before they reach the manufacturing stage
2Productivity
If automated verification system is implemented, then verification efficiency is improved, but system complexity increases
Solution Approach 1:
The patent implements a universal verification system using EDA tools that can handle multiple verification tasks simultaneously - extracting pin information, comparing with component databases, checking naming conventions, and generating verification reports. This multi-functional approach improves efficiency without proportionally increasing system complexity
Solution Approach 2:
The verification system is designed to be self-service, where the EDA tool automatically performs all verification steps without requiring complex external systems. The tool self-manages the extraction, comparison, and verification processes, reducing the overall system complexity while maintaining high verification efficiency
Data Source
AI summary
A method, a system, and a non-transitory computer readable medium for verifying pin name include storing information of a plurality of components of a circuit to be verified; running the circuit to be verified, and generating a components pin report of the components; comparing the components pin report and the stored information of the components, to determine whether names of pins of the components of the circuit to be verified are correct; when the components pin report and the stored information of the components are different, determining that the name of the pins of the components of the circuit to be verified is incorrect; and when the components pin report and the stored information of the components are the same, determining that the name of the pins of the components of the circuit to be verified is correct.


