SSD PCB Sideband Pin Remapping for Boundary Scan Access
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Solution Overview
Problem
Conventional memory devices with SSD, PCI-SIG, and SNIA form factors lack pins or pads for boundary scan testing, limiting the ability to detect issues like poor connections and manufacturing defects through electrical testing.
Innovation Solution
Remap sideband signal pins in the memory controller to create a boundary scan interface, enabling JTAG-like operations for testing by reassigning I/O connector pins to facilitate boundary scan testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional memory devices use standard form factors (SSD, PCI-SIG, SNIA), then device compatibility and standardization are improved, but the ability to perform boundary scan testing deteriorates due to lack of dedicated pins or pads
Solution Approach 1:
The patent reassigns existing sideband signal pins (SMBus, LED, MFG mode pins) to serve dual purposes: normal system operations in standard mode and boundary scan testing in JTAG mode. This multi-functionality allows the same physical pins to support both device compatibility and testing capabilities without adding extra pins, resolving the contradiction between standardization and testing ability.
Solution Approach 2:
The patent implements dynamic pin remapping where the function of pins changes based on operational mode. A remapping mechanism switches pin assignments between normal operations and boundary scan mode, allowing the system to adapt its I/O configuration dynamically. This resolves the contradiction by making the pin functionality flexible rather than fixed, enabling testing capability while maintaining standard form factor compatibility.
2Difficulty of detecting and measuring
If dedicated boundary scan pins are added to memory devices, then testing capability is improved, but device complexity and pin count increase
Solution Approach 1:
The patent eliminates the need for dedicated boundary scan pins by making existing sideband pins multi-functional. The same pins used for system management (SMBus, LED, MFG mode) are repurposed for JTAG boundary scan operations when needed. This approach provides full testing capability without increasing pin count or device complexity, as no additional hardware pins are required.
Solution Approach 2:
The patent merges the boundary scan functionality with existing sideband signal infrastructure. Instead of creating separate dedicated testing pins, the boundary scan interface is combined with the existing sideband pins, sharing the same physical resources. This merging reduces overall device complexity while maintaining comprehensive testing capability.
3Difficulty of detecting and measuring
If sideband signal pins are remapped for boundary scan operations, then testing effectiveness is improved, but normal system operations may be affected
Solution Approach 1:
The patent implements mode-based dynamic remapping where pin assignments are changed based on operational context. During normal system operations, pins maintain their standard assignments ensuring stable system function. When boundary scan testing is initiated, the remapping mechanism switches pin assignments to JTAG mode. This dynamic switching ensures that testing effectiveness is improved while system operation stability is maintained through proper mode management.
Solution Approach 2:
The patent uses periodic mode switching between normal operations and boundary scan testing. The system alternates between these two operational states, with each state having its own pin configuration. This periodic action ensures that when testing is performed, it does so with dedicated scan pin assignments, while normal operations resume with standard pin assignments, maintaining system reliability.
Data Source
AI summary
A method performed by automated test equipment (ATE) includes power cycling a solid state drive (SSD) device under test by the ATE, wherein the SSD device includes a memory controller integrated circuit (IC) attached to a printed circuit board (PCB) having a PCB interface; communicating one or more signals between the ATE and the memory controller IC using the PCB interface in a normal system mode; sending a command to cause the memory controller IC to place the PCB interface in a boundary scan mode; remapping a portion of pins of the PCB interface to a boundary scan interface; and communicating one or more boundary scan signals between the ATE and the memory controller IC using the remapped portion of pins of the PCB interface in the boundary scan mode.