3DIC Wafer Bonding and Passivation Layout to Prevent Edge Chipping
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Solution Overview
Problem
Challenges in fabricating three-dimensional integrated circuits (3DICs) include issues such as wafer edge chipping and reduced die production efficiency due to the complexity of bonding and forming passivation layers on sidewalls.
Innovation Solution
A method involving bonding a top wafer to a bottom wafer, followed by edge trimming, forming a pad layer, and etching processes to create gaps between passivation layers and metal interconnect structures, thereby preventing wafer edge chipping and enhancing die production efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bonding and passivation layer formation methods are used for 3DICs, then integration density and speed are improved, but wafer edge chipping occurs and die production efficiency decreases
Solution Approach 1:
The patent applies preliminary action by performing edge trimming on the top wafer before bonding to the bottom wafer. This pre-processing step removes potential defect sources at the wafer edges, preventing chipping during subsequent bonding and passivation processes. The edge trimming is conducted at a first thickness of the top wafer before thinning, ensuring structural integrity during the trimming operation while eliminating future reliability issues.
2Reliability
If passivation layer is formed on sidewalls of bonding pads, then electrical protection is improved, but process complexity increases
Solution Approach 1:
The patent applies local quality by forming the passivation layer selectively on specific regions rather than uniformly across the entire wafer surface. The process creates different thicknesses of the passivation layer at different locations: a first thickness on the bonding pad sidewalls for electrical protection, and a second (greater) thickness in gap regions for enhanced insulation. This localized differentiation provides targeted protection where needed while simplifying the overall process compared to complete uniform passivation.
Solution Approach 2:
The patent segments the passivation process into multiple etching stages with different masking strategies. The first etching process removes pad layer material to expose bonding pad sidewalls, while the second etching process selectively removes passivation layer material to create the desired sidewall coverage. This segmentation allows precise control over where the passivation layer is formed, achieving reliable protection without requiring overly complex single-step processes.
3Manufacturing precision
If edge trimming is performed before bonding, then wafer edge quality is improved, but additional process steps are required
Solution Approach 1:
The patent performs edge trimming as a preliminary action at an optimal point in the fabrication sequence - after the top wafer is thinned to a first thickness but before bonding to the bottom wafer. This timing allows the trimming process to effectively improve wafer edge quality and remove defects while the wafer still has sufficient structural integrity. The trimmed edges then serve as high-quality surfaces for subsequent bonding, eliminating the need for additional edge treatment steps after bonding.
Solution Approach 2:
The patent merges the edge trimming operation with the wafer thinning process by performing both operations on the top wafer before bonding. The sequence combines thickness reduction and edge quality improvement into a coordinated pre-bonding treatment phase, rather than treating them as separate post-bonding operations. This integration reduces the total number of process steps while achieving both objectives of improved manufacturing precision and process efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method reduces wafer edge chipping and significantly minimizes arcing on bonding pads, improving die production efficiency and quality.
Implementation Method 1
first bonding a top wafer to a bottom wafer
Implementation Method 2
performing a first etching process to remove part of the pad layer to form a bonding pad, and then performing a second etching process to remove part of the first passivation layer
Data Source
AI summary
A method for fabricating semiconductor device includes the steps of first bonding a top wafer to a bottom wafer, performing an edge trimming process to remove part of the top wafer, forming a pad layer on the top wafer, performing a first etching process to remove part of the pad layer to form a bonding pad, forming a first passivation layer on the bonding pad, and then performing a second etching process to remove part of the first passivation layer.