3DS FET SRAM Layout Minimizing Planar Area
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Solution Overview
Problem
Existing SRAM devices face challenges in minimizing planar area and simplifying wiring connections while maintaining high operation speed and correct operation.
Innovation Solution
The SRAM device incorporates a three-dimensional stacked (3DS) field-effect transistor (FET) with a minimized planar area and a simple wiring connection structure, featuring fin active regions with layered nano-sheets and gate electrodes that intersect these regions, enabling efficient transistor configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional SRAM device structures are used, then device operation speed and reliability are maintained, but planar area cannot be minimized and wiring connection structure becomes complex
Solution Approach 1:
The patent transitions from planar transistor arrangements to a three-dimensional stacked architecture where multiple fin active regions are vertically stacked. This vertical stacking enables multiple transistors to occupy a smaller footprint area while sharing common source/drain regions, thereby minimizing planar area. The 3DS FET structure allows gate electrodes to surround fin active regions in multiple dimensions, creating compact unit cells that reduce overall device area without increasing wiring complexity
Solution Approach 2:
The patent merges source and drain regions across multiple fin active regions by forming common source/drain regions that serve multiple transistors simultaneously. This sharing approach reduces the total number of separate source/drain contacts needed, simplifying the wiring connection structure. The shared source/drain regions are electrically connected through common contact holes, reducing the number of interconnect layers and wiring paths required
2Area of stationary object
If three-dimensional stacked FET structure is implemented, then planar area is minimized, but manufacturing complexity increases
Solution Approach 1:
The patent segments the fin active regions into multiple stacked layers, where each fin contains multiple nano-sheets arranged in series. This segmentation allows independent formation and control of each nano-sheet layer during manufacturing. The segmented structure enables selective doping and gate electrode formation for each fin, simplifying the overall fabrication process compared to forming single large-scale transistors
Solution Approach 2:
The patent implements a nested structure where multiple fin active regions are stacked vertically within a single unit cell, with each fin containing nested nano-sheets. This nesting approach allows compact integration of multiple transistor components within a small footprint. The nested arrangement shares common source/drain regions and gate electrodes across multiple fins, reducing the number of separate manufacturing steps required while maintaining the 3D stacked architecture
Data Source
AI summary
A static random-access memory (SRAM) device including a three-dimensional structured (3DS) field-effect transistor (FET) having a minimized planar area and a simple wiring connection structure includes a semiconductor substrate, a first fin active region extending on the semiconductor substrate in a first direction, a second fin active region extending on the semiconductor substrate in the first direction and apart from the first fin active region in a second direction perpendicular to the first direction, and four gates extending in the second direction and intersecting part of the first fin active region or the second fin active region. Each of the first fin active region and the second fin active region includes a first region in which only a lower layer is arranged and a second region in which an upper layer is arranged on the lower layer.