3T-2MTJ MRAM Bit Cell for TMR Readability and Area Reduction
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Solution Overview
Problem
Existing MRAMs face challenges with low and varying tunnel magneto-resistance ratio (TMR), making it difficult to distinguish between anti-parallel and parallel states, and there is a need for a faster and more energy-efficient MRAM bit cell with reduced area.
Innovation Solution
A three-transistor two-junction (3T-2MTJ) MRAM bit cell configuration is introduced, where two magnetic tunnel junctions (MTJs) are connected to bit lines through transistors, allowing for controlled current paths during reading and writing operations, enabling improved readability and reduced energy consumption by differentiating between switching events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a complementary cell with two MTJs is used to improve readability, then the tunnel magneto-resistance ratio (TMR) measurement precision is improved, but the device area increases and energy consumption increases
Solution Approach 1:
The patent merges the functions of reading and writing operations into a single unified circuit path using the 3T-2MTJ configuration. The shared path allows the same current route to serve both read and write operations, eliminating the need for separate dedicated paths and reducing overall cell area while maintaining complementary cell functionality for improved TMR measurement precision
Solution Approach 2:
The bit line and ground connector serve multiple functions: they are used for both reading operations (measuring resistance states) and writing operations (switching magnetization states). This multi-functionality reduces the number of dedicated components needed, thereby reducing cell area while maintaining the ability to distinguish between parallel and anti-parallel states through the complementary MTJ configuration
2Measurement precision
If a complementary cell with two MTJs is used to improve readability, then the TMR measurement precision is improved, but the energy consumption increases
Solution Approach 1:
The patent merges the reading and writing current paths into a single shared path through the 3T-2MTJ configuration. This allows the same current to be used for both sensing the resistance state (read) and switching the magnetization state (write), reducing the total energy required for memory operations while maintaining the complementary cell structure for improved measurement precision
Solution Approach 2:
The bit line and ground connector perform dual functions as both read and write paths. By using the same current route for both operations, the patent reduces energy consumption compared to designs with separate dedicated paths, while the complementary MTJ configuration ensures sufficient signal differentiation for accurate state detection
3Productivity
If conventional MRAM structure is used, then the device complexity is low, but the reading and writing speed is slow
Solution Approach 1:
The patent segments the bit cell into two complementary MTJs with their own dedicated transistors (first and second transistors), each controlling access to one MTJ. This segmentation allows independent control and faster switching operations for each MTJ, improving read and write speeds while the overall structure remains relatively simple and systematic
4Speed
If higher current is used to switch MTJ states, then the writing speed is improved, but the energy consumption increases
Solution Approach 1:
The third transistor acts as an intermediary element that enables efficient current distribution and control in the shared path. It facilitates faster switching by providing an additional control point for managing current flow to the MTJs, achieving high writing speeds while the shared path architecture reduces overall energy consumption compared to conventional designs
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the readability of MRAM bit cells by reducing transistor mismatch and energy consumption, allowing for faster and more efficient reading and writing operations while maintaining the ground conductor at zero potential without additional drivers or selectors.
Implementation Method 1
The tunnel magneto-resistance ratio (TMR) is a measure of the difference in resistance of the anti-parallel state and the parallel state
Implementation Method 2
opening the first transistor, i.e., bringing the transistor into a conductive state, so as to allow an electric current to flow between the first MTJ and the ground conductor
Implementation Method 3
a three transistor spin torque transfer MRAM (STT-MRAM) bit cell
Data Source
AI summary
Three transistor two junction magnetoresistive random-access memory (MRAM) bit cells provided. An example MRAM bit cell includes a first magnetic tunnel junction, MTJ, connected to a first bit line. The MRAM bit cell also includes a second MTJ connected to a second bit line. In addition, the MRAM bit cell includes a first transistor connected to the first MTJ and to a ground conductor. The MRAM bit cell further includes a second transistor connected to the second MTJ and to the ground conductor. Additionally, the MRAM bit cell includes a third transistor connected to the first transistor and to the second transistor.