Digital Storage TRIZ Cases

Row address control block generates auto-precharge signals to manage memory bank states during refresh cycles.

Adaptive reference resistance switches sense amplifier thresholds based on temperature to correct resistance drift.

A current mirror circuit uses a source-follower transistor to discharge the mirror node via charge sharing.

A perpendicular source and bitline architecture merges common source lines to reduce trace pitch in magnetic random access memory arrays.

Comparing current and previous digital values disables I/O drivers when data remains static, reducing dynamic power consumption by 40% to 75%.

Spatially weighted feedback signals adjust supply voltage across memory die areas.

Segmented digit lines and staggered activation timings resolve unused cell areas in DRAM edge arrays.

Tunnel dielectric layer segments ferroelectric gate stack to expand memory window while maintaining thickness limits.

Cross-domain control signals super-drive output transistors, reducing data output latency and settling delays in cryogenic integrated circuits.

Segmenting the sense amplifier into independently controllable primary and holding latches reduces leakage current during active idle modes.

A segmented word line driver circuit uses charge sharing to accelerate voltage rise times during read operations.

Tailored RESET pulse tails form nucleation seeds in phase change material, accelerating crystallization and reducing thermal stress during write operations.

A transfer function predicts resistance shifts in non-volatile memory cells to adjust program and read thresholds.

Write assist transistors connect inline between bit lines and ground, reducing transmission line effects and maintaining stability near minimum supply voltage.

Dynamic control signal voltage switching reduces coupling noise during sensing phases while ensuring accurate data restoration during write-back operations.

Separating demultiplexers and multiplexers into a logic base layer reduces routing length and device footprint in stacked memory arrays.

Three-transistor two-junction MRAM bit cell merges read and write paths, improving tunnel magneto-resistance measurement precision while reducing device area.

Register units store or pass data based on defect information to enable rapid memory addressing.

A semiconductor chip uses a control circuit to determine command execution sequence based on fuse-generated signals.

Depletion-type voltage drivers minimize energy consumption from over 120 pJ to about 3 pJ by reducing voltage swings during polarity transitions.

A multiferroic memory device uses voltage-driven strain to switch polarization states in ferromagnetic layers.

Multi-path semiconductor memory device routes data through independent I/O channels to resolve single-path transmission bottlenecks in multi-processor systems.

A semiconductor memory device writes only differing data values to the cell array.

A driving method controls bit line potentials in oxide semiconductor memory cells to manage transistor states during standby and read operations.

Extending state machine reset signals enables data resetting in DRAM, preventing security compromises from unreset memory cells.

A temperature compensation circuit stabilizes memristor crossbar arrays using pre-calibrated voltage adjustments.

Strategic switching buffer placement equalizes data arrival times and reduces shield line requirements in semiconductor memory layouts.

Temperature sensing blocks adjust write driver currents to resolve resistance inconsistencies across varying thermal conditions.

A wait state counter and synchronizer minimize memory access times across varying PVT conditions by ensuring reliable data readiness.

Error-prone memory stores neural network weights using inherent write errors as stochastic rounding mechanisms.

Pre-compare circuits filter search keys via population counts to selectively enable match lines, reducing power consumption from unnecessary pre-charging.

A CMOS DRAM cell uses separate NFET and PFET transistors to access a storage capacitor through distinct bit lines for reading and writing operations.

Separate rising and falling edge delay paths filter address line burrs to prevent unstable pulse widths that cause read operation failures.

Switching the data bus sense amplifier from semi-latch to full-latch mode resolves noise immunity versus current consumption trade-offs.

A reconfigurable artificial neural network uses correlated electron switches to store digital weights without in-situ training.

Alternating shared node interconnects in programmable integrated circuit memory cells reduce leakage current by 20 to 26 percent.

Back-to-back resistive memory elements paired with varistors limit programming voltage across thin gate oxide transistors.

A non-volatile memory circuit adjusts current drivability using bias signals to differentiate set and reset data states.

A memory controller selectively transmits read preambles to align data capture points with optimal timing windows.

Timing control unit uses dummy cells to generate adjustable control signals, compensating for PVT variations.

A memory device applies control signals to access transistors enabling partial electrical conductivity for current determination.

Segmented read circuits perform multiple comparisons to detect resistance states, minimizing read errors despite small sensing margins.

A write assist circuit adjusts operational voltages at memory cell terminals to accelerate transistor switching speeds.

Two-tier multiplexers and latches reduce capacitive loading while configuring into a scan chain for improved test efficiency.

A clock synchronizing circuit generates division clocks from a dynamic frequency signal to align main and data domains.

Spin transfer torque propagates domain walls along converging magnetic buses, eliminating external field requirements and reducing current consumption.

In-situ MTJ synapses execute weight computations to eliminate memory access overhead.

A semiconductor memory apparatus adjusts the temperature of a phase-change material to stabilize resistance values across multiple levels.